ADV7188BSTZ Analog Devices Inc, ADV7188BSTZ Datasheet - Page 68

• Manufacturer Part Number: ADV7188BSTZ
• Description: IC DECODER VID MULTIFORM 80LQFP
• Manufacturer: Analog Devices Inc
• Type: Video Decoderr

Specifications of ADV7188BSTZ

• Applications: Set-Top Boxes, Video Players, Recorders
• Voltage - Supply, Analog: 3.15 V ~ 3.45 V
• Voltage - Supply, Digital: 1.65 V ~ 2 V
• Mounting Type: Surface Mount
• Package / Case: 80-LQFP
• Resolution (bits): 12bit
• Input Format: Analog
• Output Format: Digital
• Adc Sample Rate: 54MSPS
• No. Of Input Channels: 12
• Supply Voltage Range: 3V To 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADV7188
VPS/PDC/UTC/Gemstar
The readback registers for VPS, PDC, and UTC are shared.
Gemstar is a high data rate standard and therefore is available
only through the ancillary stream. For evaluation purposes, any
one line of Gemstar is available through the I
the same register space as PDC, UTC, and VPS. Therefore, only
one of the following standards can be read through the I
time: VPS, PDC, UTC, or Gemstar.
To identify the data that should be made available in the I
registers, the user must program I2C_GS_VPS_PDC_UTC [1:0]
(Address 0x9C, user sub map).
I2C_GS_VPS_PDC_UTC (VDP) [1:0], Address 0x9C [6:5],
User Sub Map
These bits specify which standard result is available for I
readback.
Table 82. I2C_GS_VPS_PDC_UTC [1:0] Function
I2C_GS_VPS_PDC_UTC [1:0]
00 (default)
01
10
11
GS_PDC_VPS_UTC_CLEAR, GS/PDC/VPS/UTC Clear,
Address 0x78 [4], User Sub Map, Write Only, Self-Clearing
1—Reinitializes the GS/PDC/VPS/UTC data readback registers.
GS_PDC_VPS_UTC_AVL, GS/PDC/VPS/UTC Available,
Address 0x78 [4], User Sub Map, Read Only
0—GS, PDC, VPS, or UTC data was not detected.
1—GS, PDC, VPS, or UTC data was detected.
VDP_GS_VPS_PDC_UTC Readback Registers,
Addresses 0x84 to 0x90, User Sub Map
See Table 83.
Description
Gemstar 1×/2×
VPS
PDC
UTC
2
C registers sharing
2
2
2
C
C at a
C
Rev. A | Page 68 of 112
VPS
The VPS data bits are biphase decoded by the VDP. The
decoded data is available in both the ancillary stream and in
the I
VDP_GS_VPS_PDC_UTC_0 to VDP_VPS_PDC_UTC_12
registers (Addresses 0x84 to 0x90, user sub map). The
GS_VPS_PDC_UTC_AVL bit is set if the user had programmed
I2C_GS_VPS_PDC_UTC to 01, as explained in Table 82.
Gemstar
The Gemstar decoded data is available in the ancillary stream,
and any one line of Gemstar is available in I
evaluation purposes. To obtain the Gemstar results in the I
registers, the user must program I2C_GS_VPS_PDC_UTC to
00, as explained in Table 82.
VDP supports autodetection of Gemstar, distinguishing between
Gemstar 1× and Gemstar 2×, and decodes data accordingly. For
this autodetection mode to operate correctly, the user must set
the AUTO_DETECT_GS_TYPE I
sub map) and program the decoder to decode Gemstar 2× on
the required lines through line programming. The type of
Gemstar decoding can be determined by observing the
GS_DATA_TYPE bit (Register 0x78, user sub map).
AUTO_DETECT_GS_TYPE, Address 0x61 [4],
User Sub Map
0 (default)—Disables autodetection of Gemstar type.
1—Enables autodetection of Gemstar type.
GS_DATA_TYPE, Address 0x78 [5],
User Sub Map, Read Only
This bit identifies the decoded Gemstar data type.
0—Gemstar 1× mode is detected. Read two data bytes from 0x84.
1—Gemstar 2× mode is detected. Read four data bytes from 0x84.
The Gemstar data that is available in the I
from any line of the input video on which Gemstar was
decoded. To read the Gemstar data on a particular video line,
the user should use the manual configuration as described in
Table 67 and Table 68 and enable Gemstar decoding only on the
required line.
2
C readback registers. VPS decoded data is available in the
2
C bit (Register 0x61, user
2
C register may be
2
C registers for
2
C