MAX9526AEI+T Maxim Integrated Products, MAX9526AEI+T Datasheet - Page 11

• Manufacturer Part Number: MAX9526AEI+T
• Description: IC VID DECODER NTSC/PAL 28-QSOP
• Manufacturer: Maxim Integrated Products
• Type: Video Decoderr

Specifications of MAX9526AEI+T

• Applications: Automotive Systems, Players, TV
• Voltage - Supply, Analog: 1.8V
• Voltage - Supply, Digital: 1.8V
• Mounting Type: Surface Mount
• Package / Case: 28-QSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

A differential signal path is used to process the analog
video signal to minimize the effect of noise coupling. A
DC reference (V
and decoupled externally with a 0.1µF capacitor.
Identical signal paths and video buffers are used for
both the selected video input and the video reference
voltage. The signals are converted to a fully differential
signal by the analog AGC circuit.
The video inputs, V
MAX9526 with 0.1µF capacitors. The DC restoration cir-
cuit sets the sync level at the output of the ADC by sink-
ing or sourcing current at the selected video input. A
digital control at the ADC output is used to monitor the
average sync level. An error signal is generated in the
digital control block that is used by a current DAC to
source or sink current to the AC-coupled input to
restore the DC level. The DC restoration circuit also cor-
rects the offset in the analog signal chain and sets the
sync level at the ADC output to code 32 (decimal).
The MAX9526 includes an analog variable-gain amplifi-
er with a digitally controlled gain for automatic gain
control (AGC). The AGC uses the sync amplitude at the
output of the ADC to control the gain. For signals with-
out copy protection, the AGC adjusts the gain until the
sync amplitude is 208 (decimal) codes at the ADC out-
put. For inputs with copy protection, the AGC automati-
cally compensates for the reduced sync amplitude on
active lines.
The analog AGC loop can be disabled and the gain is
set manually to 1 of 16 values using the Gain Control
register 0x0A. The range of analog gain is 3.5dB to
12dB.
Figure 2. Sync Processing, Clock Generation, and PLL
Analog Automatic Gain Control (Analog AGC)
REF
______________________________________________________________________________________
IN1
) of 850mV is internally generated
XTAL/OSC
and V
XTAL2
IN2
, are AC-coupled to the
DC Restoration DAC
V
REF
OSCILLATOR
PROCESSING
Low-Power, High-Performance
FROM AFE
Generation
SYNC
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NTSC/PAL Video Decoder
MUX
The MAX9526 includes a high-performance anti-aliasing
analog lowpass filter with a 3dB bandwidth of 13MHz
(typ) and better than 0.25dB (typ) passband flatness to
5MHz. This eliminates the need for external filtering on
the video inputs. The filter typically provides 36dB atten-
uation at 53MHz (1MHz below ADC sample rate).
A 10-bit, 54Msps ADC converts the filtered analog
composite video signal for digital signal processing
(composite video demodulation).
Digital filtering at the ADC output removes any out-of-
band interference and improves the signal-to-noise
ratio before decoding. The signal path includes a digi-
tal anti-aliasing lowpass filter that has 1dB of passband
flatness to 5.5MHz and a minimum of 45dB of stopband
attenuation for frequencies greater than 9MHz.
The sync processing, clock generation, and PLL extract
the timing information from incoming video and gener-
ate the clock for the rest of the chip. Figure 2 shows the
block diagram for this block.
The MAX9526 includes a low-jitter crystal oscillator cir-
cuit optimized for use with an external 27MHz crystal.
The device also accepts an external CMOS logic-level
clock at either 27MHz or 54MHz. To use an external
clock (27MHz or 54MHz) instead of a crystal, set
XTAL_DIS = 1 in register 0x0D. To use a 54MHz exter-
nal clock instead of a 27MHz clock, SEL_54MHz must
also be set to 1 in register 0x0D.
MUX
Sync Processing, Clock Generation,
GENERATOR
AND PLL
CLOCK
Crystal Oscillator/Clock Input
NONSTD
VIDEO
CLOCK
Analog Lowpass Filter (LPF)
54Msps Video ADC
Digital Filtering
and PLL
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