ADV7189KST Analog Devices Inc, ADV7189KST Datasheet
ADV7189KST
Specifications of ADV7189KST
Related parts for ADV7189KST
ADV7189KST Summary of contents
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FEATURES Multiformat video decoder supports NTSC-(J, M, 4.43), PAL-(B/D/G/H/I/M/N), SECAM Integrates three 54 MHz, Noise Shaped Video®, 12-bit ADCs Clocked from a single 27 MHz crystal Line-locked clock-compatible (LLC) Adaptive-Digital-Line-Length-Tracking (ADLLT™) 5-line adaptive comb filters Proprietary architecture for locking to ...
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ADV7189 TABLE OF CONTENTS Introduction ...................................................................................... 4 Analog Front End ......................................................................... 4 Standard Definition Processor ................................................... 4 Functional Block Diagram .............................................................. 5 Specifications..................................................................................... 6 Electrical Characteristics............................................................. 6 Video Specifications..................................................................... 7 Timing Specifications .................................................................. 8 Analog Specifications................................................................... 8 Thermal Specifications ................................................................ ...
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REVISION HISTORY 3/05—Rev Rev. B Addition to Analog Specifications Section ..............................8 Change to Figure 5 ..........................................................................11 Changes to Table 9 ........................................................................14 Changes to Table 21 and Table 22 .................................................18 Clamp Operation Section Addition to Change Table 60 ........................................................................ ...
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ADV7189 INTRODUCTION The ADV7189 is a high quality, single chip, multiformat video decoder that automatically detects and converts PAL, NTSC, and SECAM standards in the form of composite, S-Video, and component video into a digital ITU-R BT.656 format. The advanced, ...
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FUNCTIONAL BLOCK DIAGRAM FORMATTER OUTPUT Figure 1. Rev Page 5 of 104 ADV7189 04819-001 ...
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ADV7189 SPECIFICATIONS Temperature range –20°C to +70°C. The min/max specifications are guaranteed over this range. MIN MAX ELECTRICAL CHARACTERISTICS VDD VDD ...
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VIDEO SPECIFICATIONS Guaranteed by characterization 3. 3. VDD temperature range, unless otherwise noted. Table 2. Parameter NONLINEAR SPECIFICATIONS Differential Phase Differential Gain Luma Nonlinearity NOISE SPECIFICATIONS SNR Unweighted Analog Front End Crosstalk LOCK TIME ...
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ADV7189 TIMING SPECIFICATIONS Guaranteed by characterization 3. 3. VDD temperature range, unless otherwise noted. Table 3. Parameter SYSTEM CLOCK AND CRYSTAL Nominal Frequency Frequency Stability PORT SCLK Frequency SCLK Min Pulse ...
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TIMING DIAGRAMS t 3 SDA SCLK OUTPUT LLC1 OUTPUT LLC2 OUTPUTS P0–P19, VS, HS, FIELD, SFL P0–P19, HS, VS, FIELD, SFL Figure Timing ...
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ADV7189 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Rating A to GND 4 V VDD A to AGND 4 V VDD D to DGND 2.2 V VDD P to AGND 2.2 V VDD D to DGND 4 V VDDIO D to ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VS HS DGND DVDDIO P15 P14 P13 P12 DGND DVDD NC SFL NC DGND DVDDIO NC P11 P10 CONNECT Table 7. Pin Function Descriptions Pin No. Mnemonic Type 3, 9, ...
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ADV7189 Pin No. Mnemonic Type 27 LLC1 O 26 LLC2 O 29 XTAL I 28 XTAL1 O 36 PWRDN ELPF I 12 SFL O 51 REFOUT O 52 CML O 48, 49 CAPY1, CAPY2 I ...
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ANALOG FRONT END ANALOG INPUT MUXING The ADV7189 has an integrated analog muxing section that allows more than one source of video signal to be connected to the decoder. Figure 6 outlines the overall structure of the input muxing provided ...
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ADV7189 SET INSEL[3:0] FOR REQUIRED MUXING CONFIGURATION Table 8. Input Channel Switching Using INSEL[3:0] INSEL[3:0] Analog Input Pins 0000 CVBS1 = AIN1 (default) 0001 CVBS2 = AIN2 0010 CVBS3 = AIN3 0011 CVBS4 = AIN4 0100 CVBS5 = AIN5 0101 ...
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Manual Input Muxing By accessing a set of manual override muxing registers, the analog input muxes of the ADV7189 can be controlled directly. This is referred to as manual input muxing. Notes • Manual input muxing overrides other input muxing ...
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ADV7189 GLOBAL CONTROL REGISTERS Register control bits listed in this section affect the whole chip. POWER-SAVE MODES Power-Down PDBP, Address 0x0F [2] There are two ways to shut down the digital core of the ADV7189: a pin ( PWRDN ) ...
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GLOBAL PIN CONTROL Three-State Output Drivers TOD, Address 0x03 [6] This bit allows the user to three-state the output drivers of the ADV7189. Upon setting the TOD bit, the P[19:0], HS, VS, FIELD, and SFL pins are three-stated. The timing ...
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ADV7189 Drive Strength Selection (Clock) DR_STR_C[1:0] Address 0x0E [3:2] The DR_STR_C[1:0] bits can be used to select the strength of the clock signal output driver (LLC pin). For more information, refer to the following sections: • Drive Strength Selection (Sync) ...
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GLOBAL STATUS REGISTERS Four registers provide summary information about the video decoder. The IDENT register allows the user to identify the revision code of the ADV7189. The other three registers contain status bits from the ADV7189. IDENTIFICATION IDENT[7:0] Address 0x11 ...
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ADV7189 STATUS 2 STATUS_2[7:0], Address 0x12 [7:0] Table 28. STATUS 2 Function STATUS 2 [7:0] Bit Name Description 0 MVCS DET Detected Macrovision color striping. 1 MVCS T3 Macrovision color striping protection. Conforms to Type 3 (if high), and Type ...
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STANDARD DEFINITION PROCESSOR (SDP) STANDARD DEFINITION PROCESSOR MACROVISION DETECTION DIGITIZED CVBS LUMA DIGITIZED Y (YC) DIGITAL FINE CLAMP DIGITIZED CVBS CHROMA DIGITIZED C (YC) DIGITAL CHROMA FINE DEMOD CLAMP F RECOVERY A block diagram of the ADV7189’s standard definition processor ...
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ADV7189 SYNC PROCESSING The ADV7189 extracts syncs embedded in the video data stream. There is currently no support for external HS/VS inputs. The sync extraction has been optimized to support imperfect video sources, for example, videocassette recorders with head switches. ...
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AD_SECAM_EN Enable Autodetection of SECAM, Address 0x07 [6] Table 32. AD_SECAM_EN Function AD_SECAM_EN Description 0 Disable the autodetection of SECAM. 1 (default) Enable the detection. AD_N443_EN Enable Autodetection of NTSC 443, Address 0x07 [5] Table 33. AD_N443_EN Function AD_N443_EN Description ...
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ADV7189 Lock Related Controls Lock information is presented to the user through Bits [1:0] of the Status 1 register. See the STATUS_1[7:0] Address 0x10 [7:0] section. Figure 9 outlines the signal flow and the controls available to influence the way ...
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COLOR CONTROLS The following registers provide user control over the picture appearance including control of the active data in the event of video being lost. They are independent of any other controls. For instance, brightness control is independent from picture ...
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ADV7189 BRI[7:0] Brightness Adjust, Address 0x0A [7:0] This register controls the brightness of the video signal through the ADV7189. Table 50. BRI Function BRI[7:0] Description (Adjust Brightness of the Picture) 0x00 (default) Offset of the luma channel = 0IRE. 0x7F ...
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CLAMP OPERATION FINE CURRENT SOURCES ANALOG VIDEO INPUT The input video is ac-coupled into the ADV7189 through a 0.1 µF capacitor recommended that the range of the input video signal is 0 1.6 V (typically 1 ...
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ADV7189 DCT[1:0] Digital Clamp Timing, Address 0x15 [6:5] The Clamp Timing register determines the time constant of the digital fine clamp circuitry important to realize that the digital fine clamp reacts very fast since it is supposed to ...
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The luma shaping filter has three control registers: • YSFM[4:0] allows the user to manually select a shaping filter mode (applied to all video signals enable an automatic selection (depending on video quality and video standard). • WYSFMOVR ...
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ADV7189 Table 60. YSFM Function YSFM[4:0] Description 0'0000 Automatic selection including a wide notch response (PAL/NTSC/SECAM) 0'0001 Automatic selection including a narrow notch response (PAL/NTSC/SECAM) 0'0010 SVHS 1 0'0011 SVHS 2 0'0100 SVHS 3 0'0101 SVHS 4 0'0110 SVHS 5 ...
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COMBINED Y ANTIALIAS, CCIR MODE SHAPING FILTER, Y RESAMPLE 0 –20 –40 –60 –80 –100 –120 FREQUENCY (MHz) Figure 13. Y S-VHS 18 Extra Wideband Filter (CCIR 601 Compliant) COMBINED Y ANTIALIAS, PAL NOTCH FILTERS, ...
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ADV7189 COMBINED C ANTIALIAS, C SHAPING FILTER, C RESAMPLER 0 –10 –20 –30 –40 –50 – FREQUENCY (MHz) Figure 16. Chroma Shaping Filter Responses GAIN OPERATION The gain control within the ADV7189 is done on ...
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Luma Gain LAGC[2:0] Luma Automatic Gain Control, Address 0x2C [7:0] The luma automatic gain control mode bits select the mode of operation for the gain control in the luma path. There are ADI internal parameters to customize the peak white ...
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ADV7189 BETACAM Enable Betacam Levels, Address 0x01 [5] If YPrPb data is routed through the ADV7189, the automatic gain control modes can target different video input levels, as outlined in Table 71. The BETACAM bit is valid only if the ...
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CG[11:0] Chroma Gain, Address 0x2D [3:0]; Address 0x2E [7:0] CMG[11:0] Chroma Manual Gain, Address 0x2D [3:0]; Address 0x2E [7:0] Chroma gain [11: dual-function register: • If written to, a desired manual chroma gain can be programmed. This gain ...
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ADV7189 CHROMA TRANSIENT IMPROVEMENT (CTI) The signal bandwidth allocated for chroma is typically much smaller than that of luminance. In the past, this was a valid way to fit a color video signal into a given overall bandwidth because the ...
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DIGITAL NOISE REDUCTION (DNR) Digital noise reduction is based on the assumption that high frequency signals with low amplitude are probably noise, and that their removal therefore improves picture quality. DNR_EN Digital Noise Reduction Enable, Address 0x4D [5] The DNR_EN ...
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ADV7189 CCMN[2:0] Chroma Comb Mode NTSC, Address 0x38 [5:3] Table 83. CCMN Function CCMN[2:0] Description 0xx (default) Adaptive comb mode. 100 Disable chroma comb. 101 Fixed chroma comb (top lines of line memory). 110 Fixed chroma comb (all lines of ...
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PAL Comb Filter Settings Used for PAL-B/G/H/I/D, PAL-M, PAL-Combinational N, PAL-60, and NTSC443 CVBS inputs PSFSEL[1:0] Split Filter Selection PAL, Address 0x19 [1:0] The NSFSEL[1:0] control selects how much of the overall signal bandwidth is fed to the combs. A ...
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ADV7189 AV CODE INSERTION AND CONTROLS 2 This section describes the I C-based controls that affect • Insertion of AV codes into the data stream • Data blanking during the vertical blank interval (VBI) • The range of data values ...
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BL_C_VBI Blank Chroma during VBI, Address 0x04 [2] Setting BL_C_VBI high, the Cr and Cb values of all VBI lines are blanked. This is done so any data that comes during VBI is not decoded as color and output through ...
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ADV7189 SYNCHRONIZATION OUTPUT SIGNALS HS Configuration The following controls allow the user to configure the behavior of the HS output pin only: • Beginning of HS signal via HSB[10:0] • End of HS signal via HSE[10:0] • Polarity of HS ...
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VS and FIELD Configuration The following controls allow the user to configure the behavior of the VS and FIELD output pins, as well as the generation of embedded AV codes: • ADV encoder-compatible signals via NEWAVMODE • PVS, PF • ...
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ADV7189 VSEHE VS End Horizontal Position Even, Address 0x33 [6] The VSEHO and VSEHE bits select the position within a line at which the VS pin (not the bit in the AV code) becomes active. Some follow-on chips require the ...
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OUTPUT VIDEO HS OUTPUT VS OUTPUT FIELD OUTPUT 262 263 264 265 OUTPUT VIDEO HS OUTPUT VS OUTPUT FIELD OUTPUT Figure 22. NTSC Typical VSync/Field Positions Using Register Writes in Table 109 Table 109. Recommended User Settings ...
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ADV7189 1 NVBEGSIGN ADVANCE BEGIN OF VSYNC BY NVBEG[4:0] NOT VALID FOR USER PROGRAMMING ODD FIELD? YES NVBEGDELO ADDITIONAL DELAY BY 1 LINE VSBHO ADVANCE BY 0.5 LINE VSYNC BEGIN Figure 23. NTSC VSync ...
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NVENDDELO NTSC VSync End Delay on Odd Field, Address 0xE6 [7] Table 114. NVENDDELO Function NVENDDELO Description 0 (default) No delay. 1 Delay VSync going low on an odd field by a line relative to NVEND. NVENDDELE NTSC VSync End ...
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ADV7189 622 623 624 625 OUTPUT VIDEO H V PVBEG[4:0] = 0x5 F PFTOG[4:0] = 0x3 310 311 312 313 OUTPUT VIDEO H V PVBEG[4: PFTOG[4:0] = 0x3 Figure 26. PAL Default (BT.656). The polarity of H, ...
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PVBEGSIGN ADVANCE BEGIN OF VSYNC BY PVBEG[4:0] NOT VALID FOR USER PROGRAMMING ODD FIELD? YES PVBEGDELO ADDITIONAL DELAY BY 1 LINE VSBHO ADVANCE BY 0.5 LINE VSYNC BEGIN Figure 28. PAL VSync Begin ...
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ADV7189 PVENDSIGN PAL VSync End Sign, Address 0xE9 [5] Table 129. PVENDSIGN Function PVENDSIGN Description 0 (default) Delay end of VSync. Set for user manual programming. 1 Advance end of VSync. Not recommended for user programming. PVEND[4:0] PAL Vsync End, ...
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VBI DATA DECODE The following low data rate VBI signals can be decoded by the ADV7189: • Wide screen signaling (WSS) • Copy generation management systems (CGMS) • Closed captioning (CCAP) • EDTV • Gemstar 1×- and 2×-compatible data recovery ...
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ADV7189 Wide Screen Signaling Data WSS1[7:0], Address 0x91 [7:0], WSS2[7:0], Address 0x92 [7:0] Figure 31 shows the bit correspondence between the analog video waveform and the WSS1/WSS2 registers. WSS2[7:6] are undetermined and should be masked out by software. RUN-IN SEQUENCE ...
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CGMS Data Registers CGMS1[7:0], Address 0x96 [7:0], CGMS2[7:0], Address 0x97 [7:0], CGMS3[7:0], Address 0x98 [7:0] Figure 33 shows the bit correspondence between the analog video waveform and the CGMS1/CGMS2/CGMS3 registers. CGMS3[7:4] are undetermined and should be masked out by software. ...
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ADV7189 Letterbox Detection Incoming video signals may conform to different aspect ratios (16:9 wide screen of 4:3 standard). For certain transmissions in the wide screen format, a digital sequence (WSS) is transmitted with the video signal WSS sequence ...
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GDECAD configures the way in which data is embedded in the video data stream. The recovered data is not available through I into the horizontal blanking period of an ITU-R BT656- compatible data stream. The data format is intended ...
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ADV7189 Table 151. Data Byte Allocation Raw Information Bytes 2× Retrieved from the Video Line Notes • DID. The data identification value is 0x140 (10-bit value). Care has been taken that in ...
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Table 152. Gemstar 2× Data, Half-Byte Mode Byte D[9] D[ ...
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ADV7189 Table 155. Gemstar 1× Data, Full-Byte Mode Byte D[9] D[ ...
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PAL CCAP Data Half-Byte output mode is selected by setting CDECAD = 0, full-byte output mode is selected by setting CDECAD = 1. See the GDECAD Gemstar Decode Ancillary Data Format, Address 0x4C [0] section. Table 158 and Table 159 ...
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ADV7189 GDECEL[15:0] Gemstar Decoding Even Lines, Address 0x48 [7:0]; Address 0x49 [7:0] The 16 bits of the GDECEL[15:0] are interpreted as a collection of 16 individual line decode enable signals. Each bit refers to a line of video in an ...
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Table 163. NTSC Line Enable Bits and Corresponding Line Numbering Line Number line[3:0] (ITU-R BT.470) Enable Bit 0 10 GDECOL[ GDECOL[ GDECOL[ GDECOL[ GDECOL[ GDECOL[ GDECOL[ ...
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ADV7189 PIXEL PORT CONFIGURATION The ADV7189 has a very flexible pixel port that can be config- ured in a variety of formats to accommodate downstream ICs. Table 167 and Table 168 summarize the various functions that the ADV7189’s pins can ...
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MPU PORT DESCRIPTION 2 The ADV7189 supports a 2-wire (I C-compatible) serial inter- face. Two inputs, serial data (SDA) and serial clock (SCLK), carry information between the ADV7189 and the system I master controller. Each slave device is recognized by ...
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ADV7189 REGISTER ACCESSES The MPU can write to or read from all of the ADV7189’s registers, except those registers that are read-only or write-only. The Subaddress register determines which register the next read or write operation accesses. All communications with ...
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I C CONTROL REGISTER MAP Table 170. Control Port Register Map Details Register Name Reset Value Input Control 0000 0000 Video Selection 1100 1000 Reserved 0000 0100 Output Control 0000 1100 Extended Output Control 0101 0101 Reserved 0000 0000 ...
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ADV7189 Table 171. Control Port Register Map Bit Details Register Name Bit 7 Bit 6 Input Control VID_SEL.3 VID_SEL.2 Video Selection ENHSPLL Reserved Output Control VBI_EN TOD Extended Output BT656-4 Control Reserved Reserved Autodetect Enable AD_SEC525_EN AD_SECAM_EN Contrast CON.7 CON.6 ...
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Register Name Bit 7 Bit 6 Gemstar Ctrl 1 GDECEL.15 GDECEL.14 Gemstar Ctrl 2 GDECEL.7 GDECEL.6 Gemstar Ctrl 3 GDECOL.15 GDECOL.14 Gemstar Ctrl 4 GDECOL.7 GDECOL.6 Gemstar Ctrl 5 CTI DNR Ctrl 1 CTI DNR Ctrl 2 CTI_C_TH.7 CTI_C_TH.6 Reserved ...
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ADV7189 REGISTER MAP DETAILS Grayed out sections mark the reset value of the register. Table 172. Register 0x00 Subaddress Register Bit Description 0x00 Input INSEL [3:0]. The INSEL bits allow the Control user to select an input ...
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Table 173. Register 0x01 Subaddress Register Bit Description 0x01 Video Reserved. Selection ENVSPROC. Reserved. BETACAM. ENHSPLL. Reserved. Bit Register Setting Set to default 0 Disable VSync processor 1 Enable ...
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ADV7189 Table 174. Register 0x03 Subaddress Register Bit Description 0x03 Output SD_DUP_AV. Duplicates the AV Control codes from the Luma into the chroma path. Reserved. OF_SEL [3:0]. Allows the user to choose from a set of output formats. TOD. Three-State ...
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Table 175. Register 0x04 Subaddress Register Bit Description 0x04 Extended RANGE. Allows the user to select Output the range of output values. Can Control be BT656 compliant, or can fill the whole accessible number range. EN_SFL_PIN. BL_C_VBI. Blank Chroma during ...
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ADV7189 Table 176. Registers 0x07 and 0x08 Subaddress Register Bit Description 0x07 Autodetect AD_PAL_EN. PAL B/G/I/H autodetect Enable enable. AD_NTSC_EN. NTSC autodetect enable. AD_PALM_EN. PAL M autodetect enable. AD_PALN_EN. PAL N autodetect enable. AD_P60_EN. PAL 60 autodetect enable. AD_N443_EN. NTSC443 ...
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Table 177. Registers 0x09 to 0x0E Subaddress Register Bit Description 0x09 Reserved Reserved. (Saturation) 0x0A Brightness BRI[7:0]. This register controls the brightness of the video signal. 0x0B Hue HUE[7:0]. This register contains the value for the color hue adjustment. 0x0C ...
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ADV7189 Table 178. Registers 0x0F to 0x11 Subaddress Register Bit Description 0x0F Power Reserved. Management PDBP. Power-down bit priority selects between PWRDN bit or PIN. Reserved. PWRDN. Power-down places the decoder in a full power-down mode. Reserved. RES. Chip Reset ...
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Table 179. Registers 0x12 to 0x13 Subaddress Register Bit Description 0x12 Status Register 2 STATUS_2[7:0]. Provides information Read-only about the internal status of the decoder. STATUS_2[5:0]. Reserved. 0x13 Status Register 3 STATUS_3[7:0]. Provides Read only information about the internal status ...
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ADV7189 Table 182. Register 0x17 Subaddress Register Bit Description 0x17 Shaping YSFM[4:0]. Selects Y Filter Shaping Filter mode Control when in CVBS only mode. Allows the user to select a wide range of low-pass and notch filters. If either automode ...
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Table 183. Registers 0x18 to 0x19 Subaddress Register Bit Description 0x18 Shaping WYSFM[4:0] Wideband Y Shaping Filter mode allows Filter the user to select which Y shaping filter is used for the Y Control 2 component of Y/C, YPbPr, B/W ...
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ADV7189 Table 184. Registers 0x27 Subaddress Register Bit Description 0x27 Pixel LTA[1:0]. Luma timing adjust Delay allows the user to specify a Control timing difference between chroma and luma samples. Reserved. CTA[2:0]. Chroma timing adjust allows a specified timing difference ...
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Table 185. Registers 0x2B to 0x2C Subaddress Register Bit Description 0x2B Misc Gain PW_UPD. Peak white update Control determines the rate of gain. Reserved. CKE. Color kill enable allows the color kill function to be switched on and off. Reserved. ...
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ADV7189 Table 186. Registers 0x2D to 0x30 Subaddress Register Bit Description 0x2D Chroma CMG[11:8]. Chroma manual Gain gain can be used to program a Control 1 desired manual chroma gain. Reading back from this register in AGC mode gives the ...
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Table 187. Register 0x31 Subaddress Register Bit Description 0x31 VS and Reserved. FIELD Control 1 HVSTIM. Selects where within a line of video the VS signal is asserted. NEWAVMODE. Sets the EAV/SAV mode. Reserved. Table 188. Registers 0x32 to 0x33 ...
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ADV7189 Table 189. Registers 0x34 to 0x36 Subaddress Register Bit Description 0x34 HS Position Control 1 HSE[10:8]. HS end allows the positioning of the HS output within the video line. Reserved. HSB[10:8]. HS begin allows the positioning of the HS ...
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Table 191. Register 0x38 Subaddress Register Bit Description 0x38 NTSC Comb YCMN[2:0]. Luma Control Comb Mode, NTSC. CCMN[2:0]. Chroma Comb Mode, NTSC. CTAPSN[1:0]. Chroma Comb Taps, NTSC. Bit Comments ...
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ADV7189 Table 192. Registers 0x39 to 0x3A Subaddress Register Bit Description 0x39 PAL Comb YCMP[2:0]. Luma Comb Control mode, PAL. CCMP[2:0]. Chroma Comb mode, PAL. CTAPSP[1:0]. Chroma comb taps, PAL. 0x3A Reserved. PWRDN_ADC_2. Enables power-down of ADC2. PWRDN_ADC_1. Enables power-down ...
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Table 193. Register 0x3D Subaddress Register Bit Description 0x3D Manual Reserved. Window CKILLTHR[2:0]. Reserved. Table 194. Registers 0x41 to 0x4C Subaddress Register Bit Description 0x41 Resample Reserved. Control SFL_INV. Controls the behavior of the PAL switch bit. Reserved. 0x48 Gemstar ...
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ADV7189 Table 195. Registers 0x4D to 0x50 Subaddress Register Bit Description 0x4D CTI DNR CTI_EN. CTI enable. Control 1 CTI_AB_EN. Enables the mixing of the transient improved chroma with the original signal. CTI_AB[1:0]. Controls the behavior of the alpha-blend circuitry. ...
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Table 196. Register 0x51 Subaddress Register Bit Description 0x51 Lock CIL[2:0]. Count-into-lock Count determines the number of lines the system must remain in lock before showing a locked status. COL[2:0]. Count-out-of-lock determines the number of lines the system must remain ...
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ADV7189 Table 197. Registers 0x8F to 0x90 Subaddress Register Bit Description 0x8F Free Run Reserved. Line Length 1 LLC_PAD_SEL [2:0]. Enables manual selection of clock for LLC1 pin. Reserved. 0x90 VBI Info WSSD. Screen signaling Read Mode detected. Details CCAPD. ...
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Table 198. Registers 0x91 to 0x9D Subaddress Register Bit Description 0x91 WSS1[7:0] WSS1[7:0]. Wide screen signaling data. Read-only. 0x92 WSS2[7:0] WSS1[7:0]. Wide screen signaling data. Read-only. 0x93 EDTV1[7:0]. EDTV1[7:0] EDTV data. Read- only. 0x94 EDTV2[7:0]. EDTV2[7:0] EDTV data. Read- only. ...
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ADV7189 Table 200. Register 0xC3 Subaddress Register Bit Description 0xC3 ADC ADC0_SW[3:0]. Manual muxing SWITCH 1 control for ADC0. ADC1_SW[3:0]. Manual muxing control for ADC1. Bit Comment ...
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Table 201. Register 0xC4 Subaddress Register Bit Description 0xC4 ADC ADC2_SW[3:0]. Manual muxing SWITCH 2 control for ADC2. Reserved. ADC_SW_MAN_EN. Enable manual setting of the input signal muxing. Bit Comments 0 0 ...
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ADV7189 Table 202. Registers 0xDC to 0xE4 Subaddress Register Bit Description 0xDC Letterbox LB_TH [4:0]. Sets the threshold value that Control 1 detects a black. Reserved. 0xDD Letterbox LB_EL[3:0]. Programs the end line of the Control 2 activity window for ...
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Table 203. Registers 0xE5 to 0xE7 Subaddress Register Bit Description 0xE5 NTSC V Bit NVBEG[4:0]. How many lines after l Begin to set V high. NVBEGSIGN. NVBEGDELE. Delay V bit going high by one line relative to NVBEG (even field). ...
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ADV7189 Table 204. Registers 0xE8 to 0xEA Subaddress Register Bit Description 0xE8 PAL V Bit PVBEG[4:0]. How many lines after l Begin to set V high. PVBEGSIGN. PVBEGDELE. Delay V bit going high by one line relative to PVBEG (even ...
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I C PROGRAMMING EXAMPLES MODE 1—CVBS INPUT (COMPOSITE VIDEO ON AIN5) All standards are supported through autodetect, 10-bit, 4:2:2, ITU-R BT.656 output on P19–P10. Table 205. Mode 1—CVBS Input Register Address Register Value 0x00 0x04 0x01 0x88 0x03 0x00 ...
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ADV7189 MODE 2—S-VIDEO INPUT (Y ON AIN1 AND C ON AIN4) All standards are supported through autodetect, 10-bit, ITU-R BT.656 output on P19–P10. Table 206. Mode 2—S-Video Input Register Address Register Value 0x00 0x06 0x01 0x88 0x03 0x00 0x2B 0xE2 ...
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MODE 4—CVBS TUNER INPUT PAL ONLY ON AIN4 10-bit, ITU-R BT.656 output on P19–P10. Table 208. Mode 4—CVBS Tuner Input PAL Only Register Address Register Value 0x00 0x83 0x03 0x00 0x07 0x01 0x17 0x41 0x19 0xFA 0x2B 0xE2 0x3A 0x16 ...
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ADV7189 PCB LAYOUT RECOMMENDATIONS The ADV7189 is a high precision, high speed mixed-signal device. To achieve the maximum performance from the part important to have a well laid-out PCB board. The following is a guide for designing a ...
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Digital Inputs The digital inputs on the ADV7189 were designed to work with 3.3 V signals, and are not tolerant signals. Extra compo- nents are needed logic signals are required to be applied to ...
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ADV7189 TYPICAL CIRCUIT CONNECTION Examples of how to connect the ADV7189 video decoder are shown in Figure 42 and Figure 43. IN AVDD_5V R43 BUFFER 0Ω R39 C93 C 4.7kΩ 100µF B FILTER Q6 R53 L10 56Ω 12µH E R38 ...
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DVDDIO AGND DGND S-VIDEO ANTI-ALIAS FILTER CIRCUIT ANTI-ALIAS FILTER CIRCUIT ANTI-ALIAS Y FILTER CIRCUIT ANTI-ALIAS Pr FILTER CIRCUIT ANTI-ALIAS Pb FILTER CIRCUIT ANTI-ALIAS CBVS FILTER CIRCUIT RECOMMENDED ANTI-ALIAS FILTER CIRCUIT IS SHOWN IN FIGURE 42 ON THE PREVIOUS PAGE. THIS ...
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... ROTATED 90° CCW ORDERING GUIDE Model Temperature Range ADV7189KST 0°C to 70°C EVAL-ADV7189BEB The ADV7189 is a Pb-free environmentally friendly product manufactured using the most up-to-date materials and processes. The coating on the leads of each device is 100% pure Sn electroplate. The device is suitable for Pb-free applications, and can withstand surface- mount soldering 255° ...
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NOTES Rev Page 103 of 104 ADV7189 ...
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ADV7189 NOTES 2 Purchase of licensed I C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I Rights to use these components system, ...