ADV7191KSTZ Analog Devices Inc, ADV7191KSTZ Datasheet - Page 36

• Manufacturer Part Number: ADV7191KSTZ
• Description: IC ENCODER VIDEO W/DAC 64LQFP
• Manufacturer: Analog Devices Inc
• Type: Video Encoderr

Specifications of ADV7191KSTZ

• Applications: DVD, PC Video, Multimedia
• Voltage - Supply, Analog: 3.3 V ~ 5 V
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Number Of Dac's: 6
• Adc/dac Resolution: 10b
• Screening Level: Commercial
• Package Type: LQFP
• Pin Count: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply, Digital: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

SUBCARRIER FREQUENCY REGISTERS 3–0
(FSC31–FSC0) (Address (SR4–SR0) = 0CH–0FH)
These 8-bit-wide registers are used to set up the Subcarrier
Frequency. The value of these registers are calculated by using
the following equation:
Figure 62 shows how the frequency is set up by the four registers.
ADV7190/ADV7191
SUBCARRIER
SUBCARRIER
SUBCARRIER
SUBCARRIER
Example: NTSC Mode, f
FREQUENCY
FREQUENCY
FREQUENCY
FREQUENCY
Subcarrier Frequency alue
REG 0
REG 2
REG 1
REG 3
Subcarrier Frequency
Figure 62. Subcarrier Frequency Registers
Subcarrier Register Value = 21F07C16 Hex
FSC15
FSC31
FSC23
FSC7
FSC14
FSC30
FSC22
FSC6
V
CLK
FSC21
FSC13
FSC29
FSC5
TIMING MODE 1 (MASTER/PAL)
TR17 TR16
= 27 MHz, f
0
0
1
1
TR17
HSYNC TO PIXEL
Register =
DATA ADJUST
=
VSYNC
HSYNC
FSC12
FSC28
FSC20
FSC4
1
0
1
(
0
2
32
0
1
2
3
–
TR16
FSC27
FSC19
FSC11
FSC3
T
T
T
T
1
PCLK
PCLK
PCLK
PCLK
)
(
SCF
2
¥
32
27
T
LINE 1
3 5795454
B
= 3.5795454 MHz
FSC10
FSC26
FSC18
–
.
FSC2
T
¥
TR15 TR14
A
f
TR15 TR14
1
CLK
RISING EDGE DELAY
0
0
1
1
10
TR15
)
HSYNC TO VSYNC
(MODE 2 ONLY)
(MODE 1 ONLY)
¥
Figure 61. Timing Register 1
VSYNC WIDTH
6
1
0
1
FSC25
FSC17
0
FSC9
FSC1
f
0
1
SCF
1
4
16
128
¥
T
T
B
B
T
T
10
FSC16
FSC24
+ 32 s
FSC0
TR14
FSC8
T
T
PCLK
PCLK
C
PCLK
T
PCLK
6
–36–
TR13 TR12
TR13
0
0
1
1
SUBCARRIER PHASE REGISTER (FPH7–FPH0)
(Address (SR4–SR0) = 10H)
This 8-bit-wide register is used to set up the Subcarrier Phase.
Each bit represents 1.41∞. For normal operation this register is
set to 00Hex.
CLOSED CAPTIONING EVEN FIELD
DATA REGISTER 1–0 (CCD15–CCD0)
(Address (SR4–SR0) = 11–12H)
These 8-bit-wide registers are used to set up the closed captioning
extended data bytes on Even Fields. Figure 64 shows how the
high and low bytes are set up in the registers.
CLOSED CAPTIONING ODD FIELD
DATA REGISTER 1–0 (CED15–CED0)
(Subaddress (SR4–SR0) = 13–14H)
These 8-bit-wide registers are used to set up the closed captioning
data bytes on Odd Fields. Figure 65 shows how the high and low
bytes are set up in the registers.
SUBCARRIER
BYTE 0
BYTE 0
VSYNC DELAY
Figure 64. Closed Captioning Extended Data Register
REGISTER
HSYNC TO
0
1
0
1
BYTE 1
BYTE 1
PHASE
0
4
8
18
Figure 65. Closed Captioning Data Register
TR12
CCD7
CED7
T
T
T
T
T
PCLK
PCLK
PCLK
B
CCD15 CCD14 CCD13 CCD12 CCD11 CCD10
CED15 CED14 CED13
Figure 63. Subcarrier Phase Register
PCLK
FPH7
T
C
CED6
CCD6
LINE 313
TR11 TR10
TR11
FPH6
0
0
1
1
HSYNC WIDTH
CED5
CCD5
1
0
1
0
FPH5
1
4
16
128
TR10
CED4
CCD4
LINE 314
T
T
T
PCLK
T
PCLK
CED12 CED11 CED10
A
PCLK
T
FPH4
PCLK
CED3
CCD3
FPH3
CED2
CCD2
FPH2
CED1
CCD1
CCD9
CED9
FPH1
CCD0
CED0
REV. B
CCD8
CED8
FPH0