CS493105-CLZ Cirrus Logic Inc, CS493105-CLZ Datasheet - Page 12

• Manufacturer Part Number: CS493105-CLZ
• Description: IC DECODER AUD MULTI STD 44PLCC
• Manufacturer: Cirrus Logic Inc
• Type: Audio Decoderr

Specifications of CS493105-CLZ

• Applications: DVD
• Voltage - Supply, Analog: 2.37 V ~ 2.63 V
• Voltage - Supply, Digital: 2.37 V ~ 2.63 V
• Mounting Type: Surface Mount
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1670

1.9. Switching Characteristics — Motorola
(VA, VD[3:1] = 2.5 V ±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, C
Notes: 1. Certain timing parameters are normalized to the DSP clock, DCLKP, in nanoseconds. DCLKP =
12
Address setup before CS and DS low
Address hold time after CS and DS low
Delay between DS then CS low or CS then DS low
Data valid after CS and DS low with R/W high
CS and DS low for read
Data hold time after CS or DS high after read
Data high-Z after CS or DS high after read
CS or DS high to CS and DS low for next read
CS or DS high to CS and DS low for next write
Delay between DS then CS low or CS then DS low
Data setup before CS or DS high
CS and DS low for write
R/W setup before CS AND DS low
R/W hold time after CS or DS high
Data hold after CS or DS high
CS or DS high to CS and DS low with R/W high for next read
CS or DS high to CS and DS low for next write
2. This specification is characterized but not production tested. A 470 ohm pull-up resistor was used for
3. See T
1/DCLK. The DSP clock can be defined as follows:
External CLKIN Mode:
DCLK == CLKIN/4 before and during boot
DCLK == CLKIN after boot
Internal Clock Mode:
DCLK == 10MHz before and during boot, i.e. DCLKP == 100ns
DCLK == 65 MHz after boot, i.e. DCLKP == 15.4ns
It should be noted that DCLK for the internal clock mode is application specific. The application code
users guide should be checked to confirm DCLK for the particular application.
characterization to minimize the effects of external bus capacitance.
mdd
from Motorola Host Mode in
Parameter
Table 7 on page 47
(Note 3)
(Note 1)
(Note 2)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
®
Host Mode
Symbol
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
mrwhld
mrwsu
mwpw
mrdtw
mcdw
mdhw
mwtrd
mrpw
mdsu
mcdr
mdhr
mdis
mwd
mas
mah
mdd
mrd
L
= 20 pF)
2*DCLKP + 10
2*DCLKP + 10
2*DCLKP + 10
2*DCLKP + 10
DCLKP + 10
DCLKP + 10
CS49300 Family DSP
Min
20
5
5
0
5
0
5
5
5
-
-
Max
21
22
∞
∞
-
-
-
-
-
-
-
-
-
-
-
-
-
DS339F7
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns