LTC1264-7CSW#PBF Linear Technology, LTC1264-7CSW#PBF Datasheet - Page 11

• Manufacturer Part Number: LTC1264-7CSW#PBF
• Description: IC FILTER 8TH ORDR LOWPASS16SOIC
• Manufacturer: Linear Technology

Specifications of LTC1264-7CSW#PBF

• Filter Type: Linear Phase, Lowpass Switched Capacitor
• Frequency - Cutoff Or Center: 200kHz
• Number Of Filters: 1
• Max-order: 8th
• Voltage - Supply: ±2.375 V ~ 8 V
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PI FU CTIO S
External Connection Pins (7, 14)
Pins 7 and 14 should be connected together. In a printed
circuit board the connection should be done under the IC
package through a short trace surrounded by the analog
ground plane.
Ratio Input Pin (10)
The DC level at this pin determines the ratio of the clock
frequency to the cutoff frequency of the filter. Pin 10 at V
gives a 25:1 ratio and pin 10 at V
single supply operation the ratio is 25:1 when pin 10 is at
V
tied to ground, it should be bypassed to analog ground
with a 0.1µF capacitor. If the DC level at pin 10 is switched
mechanically or electrically at slew rates greater than
1V/µs while the device is operating, a 10k resistor should
be connected between pin 10 and the DC source.
+
U
and 50:1 when pin 10 is at ground. When pin 10 is not
U
U
–
gives a 50:1 ratio. For
+
Clock Input Pin (11)
Any TTL or CMOS clock source with a square-wave output
and 50% duty cycle (±10%) is an adequate clock source
for the device. The power supply for the clock source
should not be the filter’s power supply. The analog ground
for the filter should be connected to clock’s ground at a
single point only. Table 7 shows the clock’s low and high
level threshold values for a dual or single supply operation.
A pulse generator can be used as a clock source provided
the high level ON time is greater than 0.1µs. Sine waves are
not recommended for clock input frequencies less than
100kHz, since excessively slow clock rise or fall times
generate internal clock jitter (maximum clock rise or fall
time ≤1µs). The clock signal should be routed from the
right side of the IC package and perpendicular to it to avoid
coupling to any input or output analog signal path. A 200Ω
resistor between clock source and pin 11 will slow down
the rise and fall times of the clock to further reduce charge
coupling (Figures 2 and 3).
Table 7. Clock Source High and Low Threshold Levels
POWER SUPPLY
Dual Supply = ±7.5V
Dual Supply = ±5V
Dual Supply = ± 2.5V
Single Supply = 12V
Single Supply = 5V
HIGH LEVEL
≥ 0.73V
≥ 7.80V
≥ 1.45V
≥ 2.18V
≥ 1.45V
LTC1264-7
LOW LEVEL
≤ – 2.0V
≤ 0.5V
≤ 0.5V
≤ 6.5V
≤ 0.5V
11
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