MF4CN-50 National Semiconductor, MF4CN-50 Datasheet - Page 7

• Manufacturer Part Number: MF4CN-50
• Description: IC LOWPASS FILTER 4TH ORD SW CAP
• Manufacturer: National Semiconductor

Specifications of MF4CN-50

• Filter Type: Butterworth, Lowpass Switched Capacitor
• Frequency - Cutoff Or Center: 20kHz
• Number Of Filters: 1
• Max-order: 4th
• Voltage - Supply: 5 V ~ 14 V
• Mounting Type: *
• Package / Case: *
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *MF4CN-50; MF4NC-50

Typical Performance Characteristics
f
vs Temperature
1.0 MF4 Application Hints
The MF4 is a non-inverting unity gain low-pass fourth-order
Butterworth switched-capacitor filter. The switched-capacitor
topology makes the cutoff frequency (where the gain drops
3.01 dB below the DC gain) a direct ratio of the clock fre-
quency supplied to the filter. Internal integrator time con-
stants set the filter’s cutoff frequency. The resistive element
of these integrators is actually a capacitor which is
“switched” at the clock frequency (for a detailed discussion
see Input Impedance Section). Varying the clock frequency
changes the value of this resistive element and thus the time
constant of the integrators. The clock-to-cutoff-frequency ra-
tio (f
pacitors
clock-to-cutoff-frequency ratio the closer this approximation
is to the theoretical Butterworth response. The MF4 is avail-
able in f
1.1 CLOCK INPUTS
The MF4 has a Schmitt-trigger inverting buffer which can be
used to construct a simple R/C oscillator. Pin 3 is connected
to V
lator’s frequency is nominally
which, is typically
for V
Note that f
as well as the resistor/capacitor tolerance (see Figure 1 ).
Schmitt-trigger threshold voltage levels can change signifi-
cantly causing the R/C oscillator’s frequency to vary greatly
from part to part.
Where accurate cutoff frequency is required, an external
clock can be used to drive the CLK R input of the MF4. This
input is TTL logic level compatible and also presents a very
light load to the external clock source ( 2 µA). With split sup-
plies and the level shift (L. Sh) tied to system ground, the
logic level is about 2V. (See the Pin Description for L. Sh).
CLK
−
/f
CLK
CC
c
which makes Pin 2 a low impedance output. The oscil-
Deviation
f
CLK
= 10V.
c
) is set by the ratio of the input and feedback ca-
CLK
in
/f
c
ratios of 50:1 (MF4-50).
is dependent on the buffer’s threshold levels
the
integrators.
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The
DC Gain Deviation
vs Power Supply Voltage
higher
the
(1)
(2)
(Continued)
7
1.2 POWER SUPPLY
The MF4 can be powered from a single supply or split sup-
plies. The split supply mode shown in Figures 2, 3 is the
most flexible and easiest to implement. Supply voltages of
±
els. Figure 4 shows AGND resistor-biased to V
supply operation. In this mode only CMOS clock logic levels
can be used, and input signals should be capacitor-coupled
or biased near mid-supply.
1.3 INPUT IMPEDANCE
The MF4 low-pass filter input (FILTER IN) is not a high im-
pedance buffer input. This input is a switched-capacitor re-
sistor equivalent, and its effective impedance is inversely
proportional to the clock frequency. The equivalent circuit of
the filter’s input can be seen in Figure 5 . The input capacitor
charges to V
the second half the charge is transferred to the feedback ca-
pacitor. The total transfer of charge in one clock cycle is
therefore Q = C
of charge per unit time, the average input current becomes
(where T equals one clock period) or
The equivalent input resistor (R
The input capacitor is 2 pF, so
The higher the clock-to-cutoff-frequency ratio, the greater
equivalent input resistance for a given clock frequency.
This input resistance will form a voltage divider with the
source impedance (R
tional to the cutoff frequency, operation at higher cutoff fre-
quencies will be more likely to load the input signal which
would appear as an overall decrease in gain to the output of
the filter. Since the filter’s ideal gain is unity, the overall gain
is given by:
5V to
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±
7V enable the use of TTL or CMOS clock logic lev-
in
during the first half of the clock period; during
in
V
in
, and since current is defined as the flow
DC Gain Deviation
vs Temperature
source
I
in
). Since R
= Q/T
in
) then can be expressed as
in
is inversely propor-
+
/2 for single
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