MCP23018-E/MJ Microchip Technology, MCP23018-E/MJ Datasheet
MCP23018-E/MJ
Specifications of MCP23018-E/MJ
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MCP23018-E/MJ Summary of contents
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... MHz • High-speed SPI interface: (MCP23S18 MHz: 2.7V ≤ V 5.5V DD ≤ • Single hardware address pin: (MCP23018) - Voltage input to allow up to eight devices on the bus • Configurable interrupt output pins: - Configurable as active-high, active-low or open-drain Block Diagram ...
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... GPB1 4 25 GPB2 5 24 GPB3 6 23 GPB4 7 22 GPB5 8 21 GPB6 9 20 GPB7 SCL 12 17 SDA DS22103A-page 2 MCP23018 GPA7 GPB0 2 GPA6 GPB1 3 GPB2 4 GPA5 GPA4 GPB3 5 GPA3 GPB4 6 GPA2 GPB5 7 GPA1 GPB6 8 GPB7 9 GPA0 V 10 INTA DD INTB SCL 11 NC SDA ...
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... Package Types: PDIP/SOIC GPB0 3 GPB1 4 GPB2 5 GPB3 6 GPB4 7 GPB5 8 GPB6 9 GPB7 SCK © 2008 Microchip Technology Inc. MCP23018/MCP23S18 MCP23S18 GPA7 26 GPA6 25 GPA5 GPB1 1 24 GPA4 GPB2 2 23 GPA3 GPB3 3 22 GPA2 GPB4 4 21 GPA1 20 GPA0 GPB5 5 19 INTA GPB6 6 18 INTB ...
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... I/O expansion for I applications. The two devices differ only in the serial interface. 2 • MCP23018 - I C interface • MCP23S18 - SPI interface The MCP23X18 consists of multiple 8-bit configuration registers for input, output and polarity selection. The system master can enable the I/Os as either inputs or outputs by writing the I/O configuration bits ...
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... Pin Descriptions 2 TABLE 1- PINOUT DESCRIPTION (MCP23018) 28L Pin 24L 24L Pin PDIP/ Name QFN SSOP Type SOIC GPB0 I/O GPB1 I/O GPB2 I/O GPB3 I/O GPB4 I/O GPB5 I/O GPB6 I/O GPB7 I SCL SDA I/O ADDR RESET INTB INTA 19 14 ...
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... MCP23018/MCP23S18 TABLE 1-2: SPI PINOUT DESCRIPTION (MCP23S18) 28L Pin 24L Pin PDIP/ Name QFN Type SOIC GPB0 3 24 I/O Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. GPB1 4 1 I/O Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor ...
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... INTFA Figure 1-1. This sequence is followed by eight bits of INTFB data from the master and an Acknowledge (ACK) from the MCP23018. The operation is ended with a stop (P) INTCAPA or restart (SR) condition being generated by the mas- INTCAPB ter. GPIOA Data is written to the MCP23018 after every byte trans- GPIOB fer ...
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... This sequence is followed by another control byte (including the Start condition and ACK) with the R/W bit equal to a logic one (R/W = 1). The MCP23018 then transmits the data contained in the addressed register. The sequence is ended with the master generating a Stop or Restart condition ...
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... FIGURE 1-1: MCP23018 I C™ DEVICE PROTOCOL - Start S - Restart Stop P - Write w - Read R - Device opcode OP ADDR - Device address - Data out from MCP23018 D OUT D - Data in to MCP23018 Byte Sequential S OP Byte S OP Sequential S OP © 2008 Microchip Technology Inc. MCP23018/MCP23S18 D IN .... W ADDR SR OP ...
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... MCP23018/MCP23S18 1.4 Multi-bit Address Decoder The ADDR pin is used to set the slave address of the 2 MCP23018 (I C only) to allow up to eight devices on the bus using only a single pin. Typically, this would require three pins. The multi-bit Address Decoder employs a basic FLASH ADC architecture (Figure 1-4) ...
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... R2=2n R2=2n © 2008 Microchip Technology Inc. MCP23018/MCP23S18 VDD= 1.8 R1=16-R2 R2/(R1+R2) V2 0.113 15 0.0625 13 0.1875 0.338 11 0.3125 0.563 0.788 9 0.4375 7 0.5625 1.013 1.238 5 0.6875 3 0.8125 1.463 1 0.9375 1.688 VDD= 2.7 R1=16-R2 R2/(R1+R2) V2 0.169 15 0.0625 13 0.1875 0.506 0.844 11 0.3125 9 0.4375 1.181 7 0.5625 1 ...
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... MCP23018/MCP23S18 FIGURE 1-4: FLASH ADC BLOCK DIAGRAM V DD analog_in adc_en gnd DS22103A-page 12 addr_out[6] d adc_en adc_en en addr_out[5] adc_en reset addr_out[4] set '0' d adc_en i2c_clk addr_out[3] adc_en addr_out[2] adc_en addr_out[1] adc_en addr_out[0] adc_en addr[6:0] i2c_addr[2:0] q adc_en q © 2008 Microchip Technology Inc. ...
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... ADDRESSING I C DEVICES (MCP23018) 2 The MCP23018 is a slave I C device that supports 7- bit slave addressing, with the read/write bit filling out the control byte. The slave address contains four fixed bits and three user-defined hardware address bits (pins A2, A1, and A0). ...
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... MCP23018/MCP23S18 2 FIGURE 1-8: I C™ ADDRESSING REGISTERS Device Opcode The ACKs are provided by the MCP23X18. FIGURE 1-9: SPI ADDRESSING REGISTERS Device Opcode DS22103A-page 14 0 ACK R Register Address 0 R Register Address ACK © 2008 Microchip Technology Inc. ...
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... OLATB 15 OL7 OL6 © 2008 Microchip Technology Inc. MCP23018/MCP23S18 The pull up resistors are individually configured and can be enabled when the pin is cofigured as an input or output. Reading the GPIOn register reads the value on the port. Reading the OLATn register only reads the latches, not the actual value on the port ...
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... MCP23018/MCP23S18 1.6 Configuration and Control Registers There are twenty two (22) registers associated with the MCP23X18 as shown in Table 1-4 and two tables show the register mapping with the two BANK bit values. Ten (10) registers are associated TABLE 1-4: CONTROL REGISTER SUMMARY (IOCON.BANK = 1) ...
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... INTCAPB 11 ICP7 ICP6 GPIOA 12 GP7 GP6 GPIOB 13 GP7 GP6 OLATA 14 OL7 OL6 OLATB 15 OL7 OL6 © 2008 Microchip Technology Inc. MCP23018/MCP23S18 bit 5 bit 4 bit 3 bit 2 IO5 IO4 IO3 IO2 IO5 IO4 IO3 IO2 IP5 IP4 IP3 IP2 IP5 IP4 IP3 IP2 ...
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... MCP23018/MCP23S18 1.6.1 I/O DIRECTION REGISTER Controls the direction of the data I/O. When a bit is set, the corresponding pin becomes an input. When a bit is clear, the corresponding pin becomes an output. REGISTER 1-3: IODIR – I/O DIRECTION REGISTER R/W-1 R/W-1 R/W-1 IO7 IO6 IO5 bit 7 ...
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... IP7:IP0: Controls the polarity inversion of the input pins <7:0> GPIO register bit will reflect the opposite logic state of the input pin GPIO register bit will reflect the same logic state of the input pin. © 2008 Microchip Technology Inc. MCP23018/MCP23S18 R/W-0 R/W-0 R/W-0 ...
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... MCP23018/MCP23S18 1.6.3 INTERRUPT-ON-CHANGE CONTROL REGISTER The GPINTEN register controls the interrupt-on- change feature for each pin bit is set, the corresponding pin is enabled for interrupt-on-change. The DEFVAL and INTCON registers must also be configured if any pins are enabled for interrupt-on-change. REGISTER 1-5: GPINTEN – INTERRUPT-ON-CHANGE PINS ...
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... DEF7:DEF0: Sets the compare value for pins configured for interrupt-on-change from defaults <7:0>. Refer to INTCON. If the associated pin level is the opposite from the register bit, an interrupt occurs. Refer to INTCON and GPINTEN. © 2008 Microchip Technology Inc. MCP23018/MCP23S18 R/W-0 R/W-0 R/W-0 DEF4 ...
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... MCP23018/MCP23S18 1.6.5 INTERRUPT CONTROL REGISTER The INTCON register controls how the associated pin value is compared for the interrupt-on-change feature bit is set, the corresponding I/O pin is compared against the associated bit in the DEFVAL register bit value is clear, the corresponding I/O pin is compared against the previous value ...
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... BANK bit is set For this reason advised to only perform byte writes to this register when changing the BANK bit. © 2008 Microchip Technology Inc. MCP23018/MCP23S18 Note: The INTB pin is not bonded out on the MCP23S18 (SPI) device in the 24-lead QFN package. The MIRROR bit must be configured to a “ ...
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... MCP23018/MCP23S18 REGISTER 1-8: IOCON – I/O EXPANDER CONFIGURATION REGISTER R/W-0 R/W-0 R/W-0 SEQOP BANK MIRROR bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 BANK: Controls how the registers are addressed (see 1 = The registers associated with each port are separated into different banks ...
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... TYPICAL PERFORMANCE CURVE FOR THE INTERNAL PULL-UP RESISTORS GPIO Pin Internal Pull-up Current vs V 400 350 300 250 200 150 100 50 0 1.5 2 © 2008 Microchip Technology Inc. MCP23018/MCP23S18 R/W-0 R/W-0 R/W-0 PU4 PU3 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared T = +25°C 2 ...
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... MCP23018/MCP23S18 1.6.8 INTERRUPT FLAG REGISTER The INTF register reflects the interrupt condition on the port pins of any pin that is enabled for interrupts via the GPINTEN register. A ‘set’ bit indicates that the associated pin caused the interrupt. This register is ‘read only’. Writes to this register will be ignored ...
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... Value at POR ‘1’ = Bit is set bit 7-0 ICP7:ICP0: Reflects the logic level on the port pins at the time of interrupt due to pin change <7:0> Logic-high Logic-low. © 2008 Microchip Technology Inc. MCP23018/MCP23S18 R-x R-x R-x ICP4 ICP3 ICP2 U = Unimplemented bit, read as ‘0’ ...
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... MCP23018/MCP23S18 1.6.10 PORT REGISTER The GPIO register reflects the value on the port. Reading from this register reads the port. Writing to this register modifies the Output Latch (OLAT) register. REGISTER 1-12: GPIO – GENERAL PURPOSE I/O PORT REGISTER R/W-0 R/W-0 R/W-0 GP7 ...
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... W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-0 OL7:OL0: Reflects the logic level on the output latch <7:0> Logic-high Logic-low. © 2008 Microchip Technology Inc. MCP23018/MCP23S18 R/W-0 R/W-0 R/W-0 OL4 OL3 OL2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
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... MCP23018/MCP23S18 1.7 Interrupt Logic If enabled, the MCP23X18 activates the INTn interrupt output when one of the port pins changes state or when a pin does not match the pre-configured default. Each pin is individually configurable as follows: • Enable/disable interrupt via GPINTEN • Can interrupt on either pin change or change from ...
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... The interrupt condition will remain as long as the condition exists, regardless if the INTAP or GPIO is read. See Figure 1-11 and Figure 1-12 for more information on interrupt operations. © 2008 Microchip Technology Inc. MCP23018/MCP23S18 FIGURE 1-11: INTERRUPT-ON-PIN- CHANGE GPx INT ACTIVE Port value Read GPIO is captured ...
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... MCP23018/MCP23S18 NOTES: DS22103A-page 32 © 2008 Microchip Technology Inc. ...
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... This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. © 2008 Microchip Technology Inc. MCP23018/MCP23S18 ..................................................................................................... -0.3V to +14V (except V and GPIOA/B) ...................................... -0. ...
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... MCP23018/MCP23S18 2.1 DC CHARACTERISTICS Operating Conditions (unless otherwise indicated): DC Characteristics 1.8V ≤ V Param Characteristic Sym No. D001 Supply Voltage V DD D002 V Start Voltage POR Ensure Power-on Reset D003 V Rise Rate Ensure Power-on Reset D004 Supply Current I DD D005 Standby (Idle) current I DDS Input Low-Voltage ...
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... POR at device power up POR 34 Tio Output Hi-impedance from Z RESET Low Note 1: This parameter is characterized, not 100% tested. 2: Data in the Typical (“Typ”) column is at 5V, +25°C, unless otherwise stated. © 2008 Microchip Technology Inc. MCP23018/MCP23S18 V DD Pin 1 kΩ 135 ≤ +125° ...
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... MCP23018/MCP23S18 TABLE 2-2: GP AND INT PINS AC Characteristics Standard Operating Conditions (unless otherwise specified) 1.8V ≤ V ≤ 5.5V at -40°C ≤ Parameter No. Sym Characteristic 50 t Serial data to output valid GPOV 51 t Interrupt pin disable time INTD input change to register valid GPIV 53 t IOC event to INT active ...
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... This parameter is characterized, not 100% tested. 2: Data in the Typical (“Typ”) column is at 5V, +25°C, unless otherwise stated.. FIGURE 2-4: HARDWARE ADDRESS LATCH TIMING adc_en i2c_addr[2:0] SCL © 2008 Microchip Technology Inc. MCP23018/MCP23S18 ≤ +125° Min Typ Max stable after — 0 — — 50 — ...
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... MCP23018/MCP23S18 2 FIGURE 2- BUS START/STOP BITS TIMING SCL 91 90 SDA START Condition Note 1: Refer to Figure 2-1 for load conditions. 2 FIGURE 2- BUS DATA TIMING 103 SCL 90 91 SDA In 109 SDA Out Note 1: Refer to Figure 2-1 DS22103A-page 38 100 101 106 107 109 for load conditions. ...
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... This parameter is characterized, not 100% tested specified from 10 to 400 (pF This parameter is not applicable in high-speed mode (3.4 MHz). © 2008 Microchip Technology Inc. MCP23018/MCP23S18 Operating Conditions (unless otherwise indicated): 1.8V ≤ V ≤ 5.5V at -40°C ≤ T ≤ +125° (SCL, SDA kΩ, C (SCL, SDA) = 135 pF ...
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... MCP23018/MCP23S18 2 TABLE 2- BUS DATA REQUIREMENTS (SLAVE MODE) (CONTINUED C™ AC Characteristics Param Characteristic No. 109 Output Valid From Clock: 100 kHz mode 400 kHz mode 3.4 MHz mode 110 Bus Free Time: 100 kHz mode 400 kHz mode 3.4 MHz mode Bus Capacitive Loading: 100 kHz and 400 kHz 3 ...
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... FIGURE 2-8: SPI OUTPUT TIMING SCK 12 SO MSB out SI © 2008 Microchip Technology Inc. MCP23018/MCP23S18 13 don’t care 2 Mode 1,1 Mode 0,0 14 LSB out DS22103A-page 41 ...
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... MCP23018/MCP23S18 TABLE 2-5: SPI INTERFACE AC CHARACTERISTICS Operating Conditions (unless otherwise indicated): SPI Interface AC Characteristics 1.8V ≤ V Param Characteristic No. Clock Frequency 1 CS Setup Time 2 CS Hold Time 3 CS Disable Time 4 Data Setup Time 5 Data Hold Time 6 CLK Rise Time 7 CLK Fall Time ...
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... PACKAGING INFORMATION 3.1 Package Marking Information 24-Lead QFN XXXXX XXXXXX XXXXXX YWWNNN 24-Lead SSOP (MCP23018 only) XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) ...
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... MCP23018/MCP23S18 Package Marking Information (Continued) 28-Lead SPDIP (300 mil) XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 28-Lead SOIC (300 mil) XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN DS22103A-page 44 Example: MCP23018 e E/SP^^ 3 0838256 Example: MCP23018 e E/SO^^ 3 YYWW NNN © 2008 Microchip Technology Inc. ...
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... Plastic Quad Flat, No Lead Package (MJ) – 4x4x0.9 mm Body [QFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2008 Microchip Technology Inc. MCP23018/MCP23S18 DS22103A-page 45 ...
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... MCP23018/MCP23S18 1RWH DS22103A-page 46 © 2008 Microchip Technology Inc. ...
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... NOTE 1RWHV © 2008 Microchip Technology Inc. MCP23018/MCP23S18 PP %RG\ >6623 φ L DS22103A-page 47 ...
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... MCP23018/MCP23S18 /HDG 6NLQQ\ 3ODVWLF 'XDO ,Q /LQH 63 ± 1RWH N NOTE 1RWHV DS22103A-page 48 PLO %RG\ >63', © 2008 Microchip Technology Inc. c ...
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... D N NOTE 1RWHV © 2008 Microchip Technology Inc. MCP23018/MCP23S18 PP %RG\ >62,& α h φ β DS22103A-page 49 ...
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... MCP23018/MCP23S18 NOTES: DS22103A-page 50 © 2008 Microchip Technology Inc. ...
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... APPENDIX A: REVISION HISTORY Revision A (September 2008) • Original Release of this Document. © 2008 Microchip Technology Inc. MCP23018/MCP23S18 DS22103A-page 51 ...
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... MCP23018/MCP23S18 NOTES: DS22103A-page 52 © 2008 Microchip Technology Inc. ...
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... MCP23018-E/SO: Extended Temp MCP23018T-E/SO: Tape and Reel, C™ Inter Interface d) MCP23018-E/SS: e) MCP23018T-E/SS: Tape and Reel, f) MCP23018-E/MJ: a) MCP23S18-E/SP: Extended Temp., b) MCP23S18-E/SO: Extended Temp., c) MCP23S18T-E/SO: Tape and Reel, d) MCP23S18T-E/MJ: Tape and Reel, Extended Temp., 28LD SPDIP package. 28LD SOIC package. Extended Temp., 28LD SOIC package. ...
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... MCP23018/MCP23S18 NOTES: DS22103A-page 54 © 2008 Microchip Technology Inc. ...
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... PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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