MCP23018-E/MJ Microchip Technology, MCP23018-E/MJ Datasheet - Page 30

• Manufacturer Part Number: MCP23018-E/MJ
• Description: IC I/O EXPANDER I2C 16B 24QFN
• Manufacturer: Microchip Technology

Specifications of MCP23018-E/MJ

• Package / Case: 24-QFN
• Interface: I²C
• Number Of I /o: 16
• Interrupt Output: Yes
• Frequency - Clock: 3.4MHz
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Logic Family: MCP23018
• Propagation Delay Time: 50 ns
• Operating Supply Voltage: 1.8 V to 5.5 V
• Power Dissipation: 700 mW
• Operating Temperature Range: - 40 C to + 125 C
• Input Voltage: 1.8 V to 5.5 V
• Logic Type: I/O Expander
• Maximum Clock Frequency: 10 MHz
• Maximum Operating Frequency: 3.4 MHz
• Mounting Style: SMD/SMT
• Output Current: 25 mA
• Output Voltage: 1.8 V to 4.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

MCP23018/MCP23S18
1.7
If enabled, the MCP23X18 activates the INTn interrupt
output when one of the port pins changes state or when
a pin does not match the pre-configured default. Each
pin is individually configurable as follows:
• Enable/disable interrupt via GPINTEN
• Can interrupt on either pin change or change from
Both conditions are referred to as Interrupt on Change
(IOC).
The Interrupt Control (INT) Module uses the following
registers/bits:
• IOCON.MIRROR - controls if the two interrupt
• GPINTEN - Interrupt enable register
• INTCON - Controls the source for the IOC
• DEFVAL - Contains the register default for IOC
1.7.1
There are two interrupt pins, INTA and INTB. By
default, INTA is associated with GPAn pins (Port A) and
INTB is associated with GPBn pins (Port B). Each port
has an independent signal which is cleared if its
associated GPIO or INTCAP register is read.
1.7.1.1
Additionally, the INTn pins can be configured to mirror
each other so that any interrupt will cause both pins to
go active. This is controlled via IOCON.MIRROR.
If IOCON.MIRROR = 0, the internal signals are routed
independently to the INTA and INTB pads.
If IOCON.MIRROR = 1, the internal signals are OR’ed
together and routed to the INTn pads. In this case, the
interrupt will only be cleared if the associated GPIO or
INTCAP is read (see
TABLE 1-6:
DS22103A-page 30
* Port n = GPIOn or INTCAPn
default as configured in DEFVAL
pins mirror each other.
operation
GPIOA and
Condition
Interrupt
GPIOA
GPIOB
GPIOB
Interrupt Logic
INTA AND INTB
Mirroring the INT pins
INTERRUPT OPERATION
(IOCON.MIRROR = 1)
Table
Read Port N*
Both Port A
and Port B
Port A
Port B
Port B
Port A
Port B
Port A
1-6).
Unchanged
Unchanged
Unchanged
Unchanged
Interupt
Result
Clear
Clear
Clear
1.7.2
If enabled, the MCP23X18 will generate an interrupt if
a mismatch condition exists between the current port
value and the previous port value. Only IOC enabled
pins will be compared. See GPINTEN and INTCON
registers.
1.7.3
If enabled, the MCP23X18 will generate an interrupt if
a mismatch occurs between the DEFVAL register and
the port. Only IOC enabled pins will be compared. See
GPINTEN, INTCON, and DEFVAL registers.
1.7.4
The INTn interrupt output can be configured as “active
low”, “active high”, or “open drain” via the IOCON
register.
Only those pins that are configured as an input (IODIR
register) with interrupt-on-change (IOC) enabled
(GPINTEN register) can cause an interrupt. Pins
defined as an output have no effect on the interrupt
output pin.
Input change activity on a port input pin that is enabled
for IOC will generate an internal device interrupt and
the device will capture the value of the port and copy it
into INTCAP.
The first interrupt event will cause the port contents to
be copied into the INTCAP register. Subsequent
interrupt conditions on the port will not cause an
interrupt to occur as long as the interrupt is not cleared
by a read of INTCAP or GPIO.
1.7.5
The interrupt will remain active until the INTCAP or
GPIO register is read (depending on IOCON.INTCC).
Writing to these registers will not affect the interrupt.
The interrupt condition will be cleared after the LSb of
the data is clocked out during a Read command of
GPIO or INTCAP (depending on IOCON.INTCC).
Note:
IOC FROM PIN CHANGE
IOC FROM REGISTER DEFAULT
INTERRUPT OPERATION
CLEARING INTERRUPTS
Assuming IOCON.INTCC = 0 (INT cleared
on GPIO read): The value in INTCAP can
be lost if GPIO is read before INTCAP
while another IOC is pending. After read-
ing GPIO, the interrupt will clear and then
set due to the pending IOC, causing the
INTCAP register to update.
© 2008 Microchip Technology Inc.