MCP23009-E/SS Microchip Technology, MCP23009-E/SS Datasheet - Page 27

• Manufacturer Part Number: MCP23009-E/SS
• Description: IC I/O EXPANDER I2C 8B 20SSOP
• Manufacturer: Microchip Technology

Specifications of MCP23009-E/SS

• Package / Case: 20-SSOP
• Interface: I²C
• Number Of I /o: 8
• Interrupt Output: Yes
• Frequency - Clock: 3.4MHz
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Logic Family: Interface ICs
• Propagation Delay Time: 50 ns
• Operating Supply Voltage: 1.8 V to 5.5 V
• Power Dissipation: 700 mW
• Operating Temperature Range: - 40 C to + 125 C
• Input Voltage: 1.8 V to 5.5 V
• Logic Type: I/O Expander
• Maximum Clock Frequency: 10 MHz
• Maximum Operating Frequency: 3.4 MHz
• Mounting Style: SMD/SMT
• Output Current: 200 mA
• Output Voltage: 0.6 V to 4.8 V
• Chip Configuration: 8 Bit
• Bus Frequency: 3.4MHz
• Ic Interface Type: I2C
• No. Of I/o's: 8
• Supply Voltage Range: 1.8V To 5.5V
• Digital Ic Case Style: SSOP
• No. Of Pins: 20
• Interface Type: I2C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

1.7
If enabled, the MCP23X09 activates the INT interrupt
output when one of the port pins changes state or when
a pin does not match the pre-configured default. Each
pin is individually configurable as follows:
• Enable/disable interrupt via GPINTEN
• Can interrupt on either pin change or change from
Both conditions are referred to as Interrupt on Change
(IOC).
The Interrupt Control Module uses the following
registers/bits:
• GPINTEN - Interrupt enable register
• INTCON - Controls the source for the IOC
• DEFVAL - Contains the register default for IOC
• IOCON (ODR and INTPOL) - configures the INT
1.7.1
If enabled, the MCP23X09 will generate an interrupt if
a mismatch condition exists between the current port
value and the previous port value. Only IOC enabled
pins will be compared. See GPINTEN and INTCON
registers.
1.7.2
If enabled, the MCP23X09 will generate an interrupt if
a mismatch occurs between the DEFVAL register and
the port. Only IOC enabled pins will be compared. See
GPINTEN, INTCON, and DEFVAL registers.
1.7.3
The INT interrupt output can be configured as “active
low”, “active high”, or “open-drain” via the IOCON
register.
Only those pins that are configured as an input (IODIR
register) with interrupt-on-change (IOC) enabled
(GPINTEN register) can cause an interrupt. Pins
configured as an output have no effect on the interrupt
output pin.
Input change activity on a port input pin that is enabled
for IOC will generate an internal device interrupt and
the device will capture the value of the port and copy it
into INTCAP.
The first interrupt event will cause the port contents to
be copied into the INTCAP register. Subsequent
interrupt conditions on the port will not cause an
interrupt to occur as long as the interrupt is not cleared
by a read of INTCAP or GPIO.
© 2009 Microchip Technology Inc.
default as configured in DEFVAL
operation
pin as push-pull, open-drain, and active level
(high or low).
Interrupt Logic
IOC FROM PIN CHANGE
IOC FROM REGISTER DEFAULT
INTERRUPT OPERATION
MCP23009/MCP23S09
1.7.4
The interrupt will remain active until the INTCAP or
GPIO register is read (depending on IOCON.INTCC).
Writing to these registers will not affect the interrupt.
The interrupt condition will be cleared after the LSb of
the data is clocked out during a Read operation of
GPIO or INTCAP (depending on IOCON.INTCC).
Note:
CLEARING INTERRUPTS
Assuming IOCON.INTCC = 0 (INT cleared
on GPIO read): The value in INTCAP can
be lost if GPIO is read before INTCAP
while another IOC is pending. After read-
ing GPIO, the interrupt will clear and then
set due to the pending IOC, causing the
INTCAP register to update.
DS22121B-page 27