CS82C55AZ Intersil, CS82C55AZ Datasheet - Page 3

• Manufacturer Part Number: CS82C55AZ
• Description: IC I/O EXPANDER 24B 44PLCC
• Manufacturer: Intersil
• Type: Programmable Peripheral Interfacer

Specifications of CS82C55AZ

• Interface: Programmable
• Number Of I /o: 24
• Interrupt Output: No
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 44-PLCC
• Chip Configuration: 8 Bit
• Bus Frequency: 8MHz
• No. Of I/o's: 24
• Supply Voltage Range: 4.5V To 5.5V
• Digital Ic Case Style: LCC
• No. Of Pins: 44
• Msl: MSL 3 - 168 Hours
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Frequency - Clock: -
• Lead Free Status / Rohs Status: RoHS Compliant part

Pin Description
Functional Diagram
SYMBOL
PB0-PB7
PC0-PC7
PA0-PA7
RESET
D0-D7
A0-A1
GND
V
WR
RD
CS
CC
SUPPLIES
POWER
BIDIRECTIONAL
RESET
D7-D0
DATA BUS
TYPE
WR
RD
CS
A1
A0
I/O
I/O
I/O
I/O
I
I
I
I
I
V
GROUND
DATA BUS: The Data Bus lines are bidirectional three-state pins connected to the system data bus.
RESET: A high on this input clears the control register and all ports (A, B, C) are set to the input mode with the “Bus
Hold” circuitry turned on.
CHIP SELECT: Chip select is an active low input used to enable the 82C55A onto the Data Bus for CPU
communications.
READ: Read is an active low input control signal used by the CPU to read status information or data via the data bus.
WRITE: Write is an active low input control signal used by the CPU to load control words and data into the 82C55A.
ADDRESS: These input signals, in conjunction with the RD and WR inputs, control the selection of one of the three
ports or the control word register. A0 and A1 are normally connected to the least significant bits of the Address Bus
A0, A1.
PORT A: 8-bit input and output port. Both bus hold high and bus hold low circuitry are present on this port.
PORT B: 8-bit input and output port. Bus hold high circuitry is present on this port.
PORT C: 8-bit input and output port. Bus hold circuitry is present on this port.
CC
3
: The +5V power supply pin. A 0.1μF capacitor between V
DATA BUS
CONTROL
BUFFER
+5V
GND
WRITE
LOGIC
READ
CONTROL
CONTROL
GROUP A
GROUP B
82C55A
INTERNAL
DATA BUS
8-BIT
DESCRIPTION
CC
and GND is recommended for decoupling.
GROUP A
GROUP A
GROUP B
GROUP B
PORT A
PORT C
PORT B
UPPER
PORT C
LOWER
(8)
(4)
(8)
(4)
PC7-PC4
PC3-PC0
PB7-PB0
PA7-PA0
I/O
I/O
I/O
I/O
November 16, 2006
FN2969.10