Z0221524ASGR50A5 Zilog, Z0221524ASGR50A5 Datasheet - Page 14

• Manufacturer Part Number: Z0221524ASGR50A5
• Description: IC MODEM CONTROLLER 44-LQFP
• Manufacturer: Zilog

Specifications of Z0221524ASGR50A5

• Data Format: V.21, V.22, V.23, Bell 103, Bell 212A
• Baud Rates: 2.4k
• Interface: Serial
• Voltage - Supply: 4.5 V ~ 5.5 V
• Mounting Type: Surface Mount
• Package / Case: 44-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PS001907-0904
Symbol
TXD/IRQ
TCLK/
HCS
RXD/HWR 31
RCLK/
HRD
V
D
DD
GND
PLCC
Pin #
29
30
32
33
34
Table 1. Pin Descriptions (Continued)
LQFP
Pin #
12
13
14
15
16
17
Single Chip Modem with Integrated Controller, Data Pump, and AFE
Function
Transmit Data
Interrupt
Request
Transmit Serial
Data Clock
Host Chip
Select
Receive Data
Host Write
Receive Serial
Data Clock
Host Read
Digital Power
Digital Ground
Input
Open
Drain
Output
Output
Input
Output
Input
Output
Input
Direction Description
Active Low, Serial mode only. Serial transmit
data to the DSP is presented on this pin.
Active Low, Parallel mode only. This pin goes
Low in response to an interrupt from the Parallel
Interface which is enabled. IRQ returns High
when the source of the interrupt is serviced, or
by disabling the interrupt.
Serial mode only. This pin is a synchronous
data clock used to transfer serial data via TXD
to the DTE. The clock frequencies are
2400,1200, and 300 Hz.
Active Low, Parallel mode only.
When this pin goes Low, data transfer between
the Z02215 Parallel Interface and the Host are
enabled. Data transfers are 8 bits wide.
Active Low, Serial mode only. The serial
receive data from the DSP is presented on this
pin.
Active Low, Parallel mode only.
On the rising edge of HWR the data on HD7–
HD0 is written to register PIDR or PISR
depending on the state of HA0 and provided
HCS is Low.
Serial mode only. This pin is a synchronous
data clock used to transfer serial data via RXD
to the DTE. The clock frequencies are 2400 Hz,
1200 Hz, and 300 Hz.
Active Low, Parallel mode only. When this pin
and HCS is Low, the contents of register PIDR
or PISR, (depending on the state of HA0), is
placed on HD7–HD0. See Table 2, “Status
Register,” on page 11
Pin Descriptions
Z02215
8