SI3015-BS Silicon Laboratories Inc, SI3015-BS Datasheet - Page 34

• Manufacturer Part Number: SI3015-BS
• Description: IC ISOMODEM LINE-SIDE 16SOIC
• Manufacturer: Silicon Laboratories Inc
• Type: Enhanced Global Direct Access Arrangementr

Specifications of SI3015-BS

• Package / Case: 16-SOIC (3.9mm Width)
• Data Format: V.90
• Interface: Serial
• Voltage - Supply: 3.3 V ~ 5 V
• Mounting Type: Surface Mount
• Product: Modem Module
• Supply Current: 0.3 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Baud Rates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant

Si3038
Slot 12: Modem GPIO Control
Slot 12 contains latency critical signals for the Si3014
and the GPIO of the Si3024. See Table 22.
Slots 3, 4, 6–9, 11: Not Used
The Si3038 always pads audio output frame slots 3, 4,
6–9, and 11 with 0s.
AC-Link Audio Input Frame (SDATA_IN)
The audio input frame data streams correspond to the
multiplexed bundles of all digital input data targeting the
AC’97 controller. This is the case with the audio output
frame; each AC-link audio input frame consists of 12
20-bit time slots. Slot 0 is a special reserved time slot
containing 16 bits that are used by the AC-link protocol
infrastructure.
Within slot 0, the first bit is a global bit (SDATA_IN slot
0, bit 15) that flags whether the Si3024 is in the Codec
Ready state or not. If the Codec Ready bit is a 0, the
Si3024 is not ready for normal operation. This condition
is normal following the deassertion of reset (e.g., while
the Si3024’s voltage references settle). When the AC-
link Codec Ready indicator bit is a 1, the AC-link and
34
GPIO15
GPIO14
GPIO13
GPIO12
GPIO11
GPIO10
GPIO9:6
GPIO5
GPIO4
GPIO3
GPIO2
GPIO1
GPIO0
Vendor Optional
Bit 3
Bit 2
Bit 1
Bit 0
GPIO
LINE2_GPIO_B
LINE2_GPIO_A
LINE2_DLCS
LINE2_CID
LINE2_RI
LINE2_OH
Reserved
LINE1_GPIO_B
LINE1_GPIO_A
LINE1_DLCS
LINE1_CID
LINE1_RI
LINE1_OH
Reserved
LINE2_FDT
LINE1_FDT
GPIO_INT
Name
Table 22. Slot 12
in/out
in/out
in
out
in
out
in/out
in/out
in
out
in
out
in
in
in
Sense
Rev. 2.01
Si3024 control and status registers are in a fully
operational state. The AC’97 controller must further
probe the Powerdown Control/Status register to
determine exactly which subsections, if any, are ready.
Before any attempts to put the Si3038 chipset into
operation, the AC’97 controller should poll the first bit in
the audio input frame (SDATA_IN slot 0, bit 15) for an
indication that the Si3024 is Codec Ready. When the
Si3024 is sampled Codec Ready, then the next 12 bit
positions sampled by the AC’97 controller indicate
which of the corresponding 12 time slots are assigned
to input data streams, and that they contain valid data.
Figure 31 illustrates the time slot-based AC-link
protocol.
A new audio input frame begins with a low to high
transition of SYNC. SYNC is synchronous to the rising
edge of BIT_CLK. On the next falling edge of BIT_CLK,
the Si3024 samples the assertion of SYNC. This falling
edge marks the time when both sides of AC-link are
aware of the start of a new audio frame.
On the next rising of BIT_CLK, the Si3024 transitions
SDATA_IN into the first bit position of slot 0 (Codec
GPIO pin B, Line 2
GPIO pin A, Line 2
Delta Loop Current Sense, Line 2
Caller ID path enable, Line 2
Caller ID path enable, Line 1
Off Hook, Line 1
Ring Detect, Line 2
Off Hook, Line 2
GPIO pin B, Line 1
GPIO pin A, Line 1
Delta Loop Current Sense, Line 1
Ring Detect, Line 1
Frame Detect, Line 2
Frame Detect, Line 1
GPIO state change
Description