SI3050-E-FM Silicon Laboratories Inc, SI3050-E-FM Datasheet - Page 59

• Manufacturer Part Number: SI3050-E-FM
• Description: IC VOICE DAA GCI/PCM/SPI 24-QFN
• Manufacturer: Silicon Laboratories Inc
• Series: -r

Specifications of SI3050-E-FM

• Function: Data Access Arrangement (DAA)
• Interface: GCI, PCM, SPI
• Number Of Circuits: 1
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 8.5mA
• Power (watts): *
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 24-WFQFN Exposed Pad
• Includes: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Si3050 + Si3011/18/19
A = 1: Response to CID command from the device using channel B2 is placed in Monitor Data.
When C = 1, bits A and B are channel enable bits. When these bits are set to 1, the individual corresponding
channels receives the command in the next command byte. The channels whose corresponding bits are set to 0
ignores the subsequent command byte.
A = 1: Channel B1 receives the command.
A = 0: Channel B1 does not receive the command.
B = 1: Channel B2 receives the command.
B = 0: Channel B2 does not receive the command.
5.42. Command Byte
The Command byte has the following structure:
RW
CMD[6:0]
The RW bit is a register read/write bit.
RW = 0: A write is performed to the Si3050’s register.
RW = 1: A read is performed on the Si3050’s register.
The CMD[6:0] bits specify the actual command to be performed.
CMD[6:0] = 0000001: Read or write a register on the Si3050.
CMD[6:0] = 0000010 – 1111111: Reserved.
5.43. Register Address Byte
The Register Address byte has the following structure:
ADDRESS[7:0]
This byte contains the actual 8-bit address of the register to be read or written.
5.44. SC Channel
The SC channel consists of six C/I bits and two handshaking bits, MR and MX. One of these channels is contained
in every 4-byte sub-frame and is transmitted every frame. The handshaking bits are described in the above Monitor
Channel section. The definition of the six C/I bits depends on the direction the bits are being sent, either
transmitted to the GCI highway bus via the DTX pin or received from the GCI highway bus via the DRX pin.
5.45. Receive SC Channel
:
LSB
MSB
5
3
0
4
7
6
2
1
CIR6
CIR5
CIR4
CIR3
CIR2
CIR1
MR
MX
C/I Bits
These bits are defined as follows:
CIR6: Reserved
CIR5: Reserved
CIR4: ONHM
CIR3: TGDE
CIR2: RG
Rev. 1.4
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