AD9995KCPZRL Analog Devices Inc, AD9995KCPZRL Datasheet - Page 17

• Manufacturer Part Number: AD9995KCPZRL
• Description: IC CCD SIGNAL PROCESSOR 56-LFCSP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 12-Bitr

Specifications of AD9995KCPZRL

• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Current - Supply: 30mA
• Mounting Type: Surface Mount
• Package / Case: 56-LFCSP
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Input Voltage Range: 0.5V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 12b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 56
• Package Type: LFCSP EP
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Vertical Pattern Groups (VPAT)
The vertical pattern groups define the individual pulse patterns
for each V1–V6 output signal. Table V summarizes the registers
available for generating each of the 10 V-pattern groups. The start
polarity (VPOL) determines the starting polarity of the vertical
sequence, and can be programmed high or low for each V1–V6
output. The first, second, and third toggle position (VTOG1,
VTOG2, VTOG3) are the pixel locations within the line where
the pulse transitions. A fourth toggle position (VTOG4) is also
available for V-Pattern Groups 8 and 9. All toggle positions are
12-bit values, allowing their placement anywhere in the hori-
zontal line. A separate register, VPATSTART, specifies the start
position of the V-pattern group within the line (see the Vertical
Sequences section). The VPATLEN register designates the total
Register
VPOL
VTOG1
VTOG2
VTOG3
VTOG4
VPATLEN
FREEZE1
RESUME1
FREEZE2
RESUME2
REV. 0
HD
V2
V6
V1
PROGRAMMABLE SETTINGS FOR EACH V-PATTERN:
1. START POLARITY
2. FIRST TOGGLE POSITION
3. SECOND TOGGLE POSITION (3RD TOGGLE POSITION ALSO AVAILABLE, 4TH TOGGLE POSITION AVAILABLE FOR V-PATTERN GROUPS 8 AND 9)
4. TOTAL PATTERN LENGTH FOR ALL V1-V6 OUTPUTS
Length
1b
12b
12b
12b
12b
12b
12b
12b
12b
12b
1
1
1
START POSITION OF V-PATTERN GROUP IS PROGRAMMABLE IN V-SEQUENCE REGISTERS
Range
High/Low
0–4096 Pixel Location
0–4096 Pixel Location
0–4096 Pixel Location
0–4096 Pixel Location
0–4096 Pixels
0–4096 Pixel Location
0–4096 Pixel Location
0–4096 Pixel Location
0–4096 Pixel Location
2
Figure 16. Vertical Pattern Group Programmability
2
2
4
Table V. Vertical Pattern Group Registers
3
3
3
–17–
Description
Starting Polarity of Each V1–V6 Output
First Toggle Position within Line for Each V1–V6 Output
Second Toggle Position within Line for Each V1–V6 Output
Third Toggle Position within Line for Each V1–V6 Output
Fourth Toggle Position, only Available in V-Pattern Groups 8 and 9
Total Length of Each V-Pattern Group
Holds the V1–V6 Outputs at Their Current Levels (Static DC)
Resumes Operation of the V1–V6 Outputs to Finish Their Pattern
Holds the V1–V6 Outputs at Their Current Levels (Static DC)
Resumes Operation of the V1–V6 Outputs to Finish Their Pattern
length of the V-pattern group, which will determine the number
of pixels between each of the pattern repetitions, when repetitions
are used (see the Vertical Sequences section).
The FREEZE and RESUME registers are used to temporarily
stop the operation of the V1–V6 outputs. At the pixel location
specified in the FREEZE register, the V1–V6 outputs will be
held static at their current dc state, high or low. The V1–V6
outputs are held until the pixel location specified by RESUME
register. Two sets of FREEZE/RESUME registers are pro-
vided, allowing the vertical outputs to be interrupted twice in
the same line. The FREEZE and RESUME positions are pro-
grammed in the V-pattern group registers, but are separately
enabled using the VMASK registers, which are described in the
Vertical Sequence section.
AD9995