DS1876T+T&R Maxim Integrated Products, DS1876T+T&R Datasheet - Page 20

• Manufacturer Part Number: DS1876T+T&R
• Description: IC CTRLR SFP DUAL LDD 28TQFN
• Manufacturer: Maxim Integrated Products
• Type: SFP Laser Controllerr

Specifications of DS1876T+T&R

• Input Type: Logic
• Output Type: Logic
• Interface: I²C
• Current - Supply: 10mA
• Mounting Type: Surface Mount
• Package / Case: 28-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SFP Controller with Dual LDD Interface
Figure 12. I
20
SDA
SCL
NOTE: TIMING IS REFERENCED TO V
Byte Write: A byte write consists of 8 bits of informa-
tion transferred from the master to the slave (most
significant bit first) plus a 1-bit acknowledgement from
the slave to the master. The 8 bits transmitted by the
master are done according to the bit write definition
and the acknowledgement is read using the bit read
definition.
of SCL during a bit read. The device shifts out each
bit of data on SDA at the falling edge of the previous
SCL pulse and the data bit is valid at the rising edge
of the current SCL pulse. Remember that the master
generates all SCL clock pulses, including when it is
reading bits from the slave.
Acknowledgement (ACK and NACK): An acknowl-
edgement (ACK) or not-acknowledge (NACK) is
always the 9th bit transmitted during a byte transfer.
The device receiving data (the master during a read
or the slave during a write operation) performs an ACK
by transmitting a zero during the 9th bit. A device per-
forms a NACK by transmitting a one during the 9th bit.
Timing (Figure 12) for the ACK and NACK is identical
to all other bit writes. An ACK is the acknowledgment
that the device is properly receiving data. A NACK is
used to terminate a read sequence or as an indication
that the device is not receiving data.
Byte Read: A byte read is an 8-bit information transfer
from the slave to the master plus a 1-bit ACK or NACK
from the master to the slave. The 8 bits of information
that are transferred (most significant bit first) from the
slave to the master are read by the master using the
_____________________________________________________________________________________
STOP
2
t
BUF
C Timing
START
t
HD:STA
IL(MAX)
t
LOW
AND V
IH(MIN)
t
R
.
t
HD:DAT
t
HIGH
t
F
t
SU:DAT
REPEATED
bit read definition, and the master transmits an ACK
using the bit write definition to receive additional data
bytes. The master must NACK the last byte read to
terminate communication so the slave returns control
of SDA to the master.
Slave Address Byte: Each slave on the I
responds to a slave address byte sent immediately
following a START condition. The slave address byte
contains the slave address in the most significant 7 bits
and the R/W bit in the least significant bit.
The DS1876 responds to three slave addresses. The
auxiliary memory always responds to a fixed I
address, A0h. (If the main device’s slave address
is programmed to be A0h, access to the auxiliary
memory is disabled.) The Lower Memory and Tables
00h–06h respond to I
3 bits are configurable (A0h–AEh, B0h-BEh) using the
DEVICE ADDRESS byte (Table 02h, Register 8Bh). The
user also must set the ASEL bit (Table 02h, Register
88h) for this address to be active. By writing the cor-
rect slave address with R/W = 0, the master indicates
it writes data to the slave. If R/W = 1, the master reads
data from the slave. If an incorrect slave address is
written, the DS1876 assumes the master is communi-
cating with another I
munications until the next START condition is sent.
Memory Address: During an I
to the DS1876, the master must transmit a memory
address to identify the memory location where the
slave is to store the data. The memory address is
START
t
SU:STA
t
HD:STA
2
2
C device and ignores the com-
C slave addresses whose lower
t
SP
2
C write operation
t
SU:STO
2
2
C slave
C bus