AD9822JRS Analog Devices Inc, AD9822JRS Datasheet - Page 15

• Manufacturer Part Number: AD9822JRS
• Description: IC CCD SIGNAL PROC 14BIT 28-SSOP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 14-Bitr

Specifications of AD9822JRS

• Rohs Status: RoHS non-compliant
• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Current - Supply: 73mA
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP
• Analog Front End Type: CCD/CIS
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Sample Rate: 15MSPS
• Input Voltage Range: 1V
• Operating Supply Voltage (min): 3/4.75V
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Resolution: 14b
• Supply Current: 4/73mA
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 28
• Package Type: SSOP
• Number Of Channels: 3
• Lead Free Status / RoHS Status: Not Compliant

CIRCUIT OPERATION
ANALOG INPUTS—CDS MODE
Figure 10 shows the analog input configuration for the CDS
mode of operation. Figure 11 shows the internal timing for the
sampling switches. The CCD reference level is sampled when
CDSCLK1 transitions from high to low, opening S1. The CCD
data level is sampled when CDSCLK2 transitions from high to
low, opening S2. S3 is then closed, generating a differential
output voltage representing the difference between the two
sampled levels.
The input clamp is controlled by CDSCLK1. When CDSCLK1 is
high, S4 closes and the internal bias voltage is connected to the
analog input. The bias voltage charges the external 0.1 µF input
capacitor, level-shifting the CCD signal into the AD9822’s input
common-mode range. The time constant of the input clamp is
determined by the internal 5 kΩ resistance and the external
0.1 µF input capacitance.
(INTERNAL)
Figure 10. CDS Mode Input Configuration (All Three Channels are Identical)
CDSCLK1
CDSCLK2
CCD SIGNAL
Q3
1µF
S1, S4 CLOSED
+
Figure 11. CDS Mode Internal Switch Timing
0.1µF
C
IN
OFFSET
S1, S4 OPEN
S2 OPEN
S3 OPEN
0.1µF
VINR
S2 CLOSED
AD9822
S4
S3 CLOSED
5kΩ
4V
3V
AVDD
S1, S4 CLOSED
1.7kΩ
2.2kΩ
6.9kΩ
S2
S1
INPUT CLAMP LEVEL
IS SELECTED IN THE
CONFIGURATION
REGISTER.
S3
S2 CLOSED
2pF
2pF
S3 CLOSED
CML
CML
Rev. B | Page 15 of 20
EXTERNAL INPUT COUPLING CAPACITORS
The recommended value for the input coupling capacitors is
0.1 µF. While it is possible to use a smaller capacitor, this larger
value is chosen for several reasons:
• Signal Attenuation: The input coupling capacitor creates a
• Linearity: Some of the input capacitance of a CMOS IC is
• Sampling Errors: The internal 2 pF sample capacitors have a
capacitive divider with a CMOS integrated circuit’s input
capacitance, attenuating the CCD signal level. CIN should be
large relative to the IC’s 10 pF input capacitance in order to
minimize this effect.
junction capacitance, which varies nonlinearly with applied
voltage. If the input coupling capacitor is too small, the
attenuation of the CCD signal varies nonlinearly with signal
level. This degrades the system linearity performance.
“memory” of the previously sampled pixel. There is a charge
redistribution error between CIN and the internal sample
capacitors for larger pixel-to-pixel voltage swings. As the
value of CIN is reduced, the resulting error in the sampled
voltage increases. With a CIN value of 0.1 µF, the charge
redistribution error is less than 1 LSB for a full-scale, pixel-to-
pixel voltage swing.
AD9822