AD9843AJSTRL Analog Devices Inc, AD9843AJSTRL Datasheet - Page 11

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AD9843AJSTRL

Manufacturer Part Number
AD9843AJSTRL
Description
IC CCD SIGNAL PROC 10BIT 48-LQFP
Manufacturer
Analog Devices Inc
Type
CCD Signal Processor, 10-Bitr
Datasheet

Specifications of AD9843AJSTRL

Rohs Status
RoHS non-compliant
Input Type
Logic
Output Type
Logic
Interface
3-Wire Serial
Mounting Type
Surface Mount
Package / Case
48-LQFP
Current - Supply
-
0
D10
X
D10
X
D10
X
D10
X
D10
Must be set to zero.
Must be set to zero.
Control Register Bit D3 must be set high for the CDS Gain Register to be used.
When D3 = 0 (CDS Gain Disabled), the CDS Gain Register is fixed at 4 dB (Code 63 dec).
Data Out
D9
0 Enable
1 Three-State
D9
0
MSB
D9
0
1
1
D9
X
D9
X
D8
0
D8
0
1
1
D8
X
D8
X
Set to one.
D7
1
D8
0
MSB
D7
0
0
0
1
1
D7
0
1
1
D7
X
D7
0
D6
0
Table IV. Clamp Level Register Contents (Default Value x080)
Table III. VGA Gain Register Contents (Default Value x096)
Table VI. CDS Gain Register Contents (Default Value x000)
Table II. Operation Register Contents (Default Value x000)
Table V. Control Register Contents (Default Value x000)
D6
0
0
0
1
1
DATACLK
D6
0 Rising Edge Trigger
1 Falling Edge Trigger
Optical Black Clamp
D5
0 Enable Clamping
1 Disable Clamping
D6
1
1
1
D6
X
D5
0
0
0
1
1
D5
0
1
1
MSB
D5
0
0
1
1
D4
0
0
0
1
1
D4
1
1
1
D4
0
1
0
1
CLP/PBLK
D5
0 Active Low
1 Active High
Reset
D4
0 Normal
1 Reset All
D3
1
1
0
0
0
Registers
to Default 1
D3
1
1
1
D3
0
1
0
1
D2
0
0
0
1
1
Power-Down Modes
D3 D2
0
0
1
D2
1
1
1
SHP/SHD
D4
0 Active Low
1 Active High 1 Enabled
D2
0
1
0
1
0 Standby
0 Normal Power
1 Fast Recovery
1 Total Power-Down 1
D1
0
0
1
1
1
D1
1
1
1
D1
0
1
0
1
LSB
D0
0
1
0
0
1
CDS Gain
D3
0 Disabled
LSB
D0
1
0
1
LSB
D0
0
0
0
1
Channel Selection
D1 D0
0
0
1
Clamp Level (LSB)
0
0.25
0.5
63.5
63.75
0
1
0
1
AD9843A
Gain (dB)
2.0
35.965
36.0
D2
0
Gain (dB)
+4.3
+10.0
–2.0
+4.0
CCD-Mode
AUX1-Mode
AUX2-Mode
Test Only
D1
0
D0
0

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