DS32EL0421SQE/NOPB National Semiconductor, DS32EL0421SQE/NOPB Datasheet - Page 23

• Manufacturer Part Number: DS32EL0421SQE/NOPB
• Description: IC SERIALIZER DDR LVDS PAR 48LLP
• Manufacturer: National Semiconductor

Specifications of DS32EL0421SQE/NOPB

• Function: Serializer
• Data Rate: 3.125Gbps
• Input Type: LVDS
• Output Type: CML
• Number Of Inputs: 5
• Number Of Outputs: 1
• Voltage - Supply: 2.5V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LLP
• Leaded Process Compatible: Yes
• Rohs Compliant: Yes
• Peak Reflow Compatible (260 C): Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DS32EL0421SQETR

26
27
28
29
2A
(Hex)
Addr
LVDS Operation 7:2
Event Disable
Loss of Signal
Power Down
Event Status
Status
Name
7
6
5
4
3
2
1
0
7:5
4
3
2
1
0
1
0
7:6
5
4:0
7:4
3
2
1:0
Bits
Channel Reset
Clock
Powerdown
LVDS Clock
enable
TxIN4 Enable
TxIN3 Enable
TxIN2 Enable
TxIN1 Enable
TxIN0 Enable
Reserved
PLL Lock
Disable
FIFO Error
Disable
Parallel Clock
Detect Disable
Clock Loss of
Signal Disable
Data Loss of
Signal Disable
Reserved
LVDS Loss of
Signal Preset
LVDS Loss of
Signal Reset
Reserved
Clock Loss of
Signal
Data Loss of
Signal
Reserved
TxCLKIN Detect
Reserved
Link Detect 1:0
Field
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
23
Default
1'b
1'b
1'b
1'b
1'b
1'b
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1: Reset high speed channel. Self-clearing bit.
1: Power down parallel, parallel-to-serial, and always
on clock
0: Disable TxCLKIN
1: Enable TxCLKIN
0: Disable TxIN4
1: Enable TxIN4
0: Disable TxIN3
1: Enable TxIN3
0: Disable TxIN2
1: Enable TxIN2
0: Disable TxIN1
1: Enable TxIN1
0: Disable TxIN0
1: Enable TxIN0
0: Count clock errors
1: Clock error count disabled
0: Count FIFO erros 1: FIFO error count disabled
0: Count clock detect errors
1: Clock detect count disabled
0: Count clock los of signal errors
1: Clock loss of signal count disabled
0: Count data los of signal errors
1: Clock data of signal count disabled
1: Preset signal for LVDS loss of signal register
1: Clear signal for LVDS loss of signal register
0: Clock present
1: No clock present on TxCLKIN
0: Data present
1: No data present on TxIN4:0
0: TxCLKIN not detected
1: TxCLKIN detected
0: Link not detected
1: Link detected
Description
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