DS32EL0421SQE/NOPB National Semiconductor, DS32EL0421SQE/NOPB Datasheet - Page 24

• Manufacturer Part Number: DS32EL0421SQE/NOPB
• Description: IC SERIALIZER DDR LVDS PAR 48LLP
• Manufacturer: National Semiconductor

Specifications of DS32EL0421SQE/NOPB

• Function: Serializer
• Data Rate: 3.125Gbps
• Input Type: LVDS
• Output Type: CML
• Number Of Inputs: 5
• Number Of Outputs: 1
• Voltage - Supply: 2.5V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LLP
• Leaded Process Compatible: Yes
• Rohs Compliant: Yes
• Peak Reflow Compatible (260 C): Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DS32EL0421SQETR

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2B
2C
2D Reserved
2E
2F
30
31–68 Reserved
(Hex)
Addr
Analog Driver
Event Config
Event Count
Clock Delay
Tx Config
Name
7
6
5
4
3
2
1
0
7:0
7
6
5:2
1
0
7:6
5
4
3
2
1
0
7:5
4:0
Bits
Reserved
PLL Lock Event
Link Event
Loss of Signal
Event
Event Count
Select
Clear PLL Error
Count
Clear Link Error
Count
Enable Count
Event Counter
Reserved
Reverse Data
Order
Reserved
Link Detect 1
Link Detect 0
Reserved
Output
Termination
Link Start
Link Stop
TxOUT Override
TxOUT1 Enable
TxOOUT0
Enable
TxCLKIN Delay
Reserved
Field
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
24
00010’b
Default
011’b
1'b
1'b
1'b
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0: Count PLL lock events
1: Do not count PLL lock events
0: Count link events
1: Do not count link events
0: Count loss of signal events
1: Do not count loss of signal events
0: Select PLL event count for reading
1: Select link event count for reading
1: Reset PLL error count. Self clearing bit.
1: Reset link error count. Self clearing bit.
0: Disable event counters
1: Enable event counters
0: Normal
1: Reverse output data order
Link detect value for channel 1
Link detect value for channel 0
0: 75 Ω terminations
1: 50 Ω terminations
0: Start when TxOUT0 or TxOUT1 link
1: Start when TxOUT0 and TxOUT1 linke
0: Stop when TxOUT0 and TxOUT1 both links invalid
1: Stop when TxOUT0 or TxOUT1 break link, either
link is invalid
0: TxOUT0 enabled by default, TxOUT1_en pin
controls channel1
1: Override enable of TxOUT0 and TxOUT1
0: TxOUT1 disabled
1: TxOUT1 enabled
For proper operation of TxOUT1, the TxOUT1_EN pin
must be held high.
0: TxOUT0 disabled
1: TxOUT0 enabled
000: Min clock delay, 350 ps
011: 725 ps
111: Max clock delay, 1225 ps
Description