DS92LV1212TMSA National Semiconductor, DS92LV1212TMSA Datasheet - Page 10

• Manufacturer Part Number: DS92LV1212TMSA
• Description: IC DESERIALZR RANDOM LOCK 28SSOP
• Manufacturer: National Semiconductor

Specifications of DS92LV1212TMSA

• Function: Deserializer
• Data Rate: 400Mbps
• Input Type: LVDS
• Output Type: LVDS
• Number Of Inputs: 1
• Number Of Outputs: 10
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *DS92LV1212TMSA

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AC Timing Diagrams and Test Circuits
SW - Setup and Hold Time (Internal data sampling window)
t
t
Application Information
Using the DS92LV1021 and DS92LV1212
The Serializer and Deserializer chipset is an easy to use
transmitter and receiver pair that sends 10 bits of parallel
TTL data over a serial Bus LVDS link up to 400 Mbps. Seri-
alization of the input data is accomplished using an onboard
PLL at the Serializer which embeds two clock bits with the
data. The Deserializer uses a separate reference clock
(REFCLK) and an onboard PLL to extract the clock informa-
tion from the incoming data stream and deserialize the data.
The Deserializer monitors the incoming clock information to
determine lock status and will indicate loss of lock by raising
the LOCK output.
Power Considerations
All CMOS design of the Serializer and Deserializer makes
them inherently low power devices. Additionally, the constant
current source nature of the Bus LVDS outputs minimize the
slope of the speed vs. I
Powering Up the Deserializer
The DS92LV1212 can be powered up at any time following
the proper sequence. The REFCLK input can be running be-
fore the Deserializer is powered up and it must be running in
order for the Deserializer to lock to incoming data. The Dese-
rializer outputs will remain in TRI-STATE until the Deserial-
izer detects data transmission at its inputs and locks to the
incoming stream. The recommended power up sequence for
the Deserializer is to power up all V
with the PWRDWN pin held low for 1µs. Once the V
have stabilized the Deserializer is ready for locking. Another
option to ensure proper power up is to cycle the PWRDWN
pin from high to low and back to high after power up.
Transmitting Data
Once the Serializer and Deserializer are powered up and
running they must be phase locked to each other in order to
transmit data. Phase locking is accomplished by the Deseri-
alizer locking to incoming data or by the Serializer sending
SYNC patterns to the Deserializer. SYNC patterns are sent
by the Serializer whenever SYNC1 or SYNC2 inputs are
held high. The LOCK output of the Deserializer is high when-
ever the Deserializer is not locked. Connecting the LOCK
output of the Deserializer to one of the SYNC inputs of the
Serializer will guarantee that enough SYNC patterns are
sent to achieve Deserializer lock.
The Deserializer can also be locked by simply powering up
the device and allowing the “random lock” circuitry to find
and lock to the data stream for the Serializer.
JIT
RSM
- Serializer Output Bit Position Jitter
= Receiver Sampling Margin Time
CC
curve of CMOS designs.
CC
FIGURE 9. Receiver Bus LVDS Input Skew Margin
pins simultaneously
CC
pins
10
(Continued)
While the Deserializer LOCK output is low, data at the Dese-
rializer outputs (ROUT0-9) is valid except for the specific
case of loss of lock during transmission.
Noise Margin
The Deserializer noise margin is the amount of input jitter
(phase noise) that the Deserializer can tolerate and still reli-
ably receive data. Various environmental and systematic fac-
tors include:
out-of-band noise)
Recovering from LOCK Loss
In the case where the Serializer loses lock during data trans-
mission up to 5 cycles of data that was previously received
can be invalid. This is due to the delay in the lock detection
circuit. The lock detect circuit requires that invalid clock infor-
mation be received 4 times in a row to indicate loss of lock.
Since clock information has been lost it is possible that data
was also lost during these cycles. When the Deserializer
LOCK pin goes low, data from at least the previous 5 cycles
should be resent upon regaining lock.
Lock can be regained at the Deserializer by causing the Se-
rializer to resend SYNC patterns as described above or by
random lock which can take more time depending upon the
data patterns being received.
Input Failsafe
In the event that the Deserializer is disconnected from the
Serializer, the failsafe circuitry is designed to reject certain
amount of noise from being interpreted as data or clock. The
outputs will be tri-stated and the Deserializer will lose lock.
Hot Insertion
All the BLVDS devices are hot pluggable if you follow a few
rules. When inserting, ensure the Ground pin(s) makes con-
tact first, then the VCC pin(s), then the I/O pins. When re-
moving, the I/O pins should be unplugged first, then the
VCC, then the Ground. Random lock hot insertion is illus-
trated in Figure 10 .
PCB Considerations
The Bus LVDS devices Serializer and Deserializer should be
placed as close to the edge connector as possible. In mul-
tiple Deserializer applications, the distance from the Deseri-
alizer to the slot connector appears as a stub to the Serial-
izer driving the backplane traces. Longer stubs lower the
impedance of the bus increasing the load on the Serializer
Serializer: TCLK jitter, V
Media: ISI, V
Deserializer: V
CM
CC
noise
DS100982-21
noise
CC
noise (noise bandwidth and