ISL54100CQZ Intersil, ISL54100CQZ Datasheet
ISL54100CQZ
Specifications of ISL54100CQZ
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ISL54100CQZ Summary of contents
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... All other trademarks mentioned are the property of their respective owners. FN6275 software-controlled operation 4X2 TMDS TX TMDS OUT 4X2 TMDS TX TMDS OUT 4X2 TMDS TX TMDS OUT Intersil (and design registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006-2008. All Rights Reserved ...
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... PART NUMBER NUMBER OF (Note) CHANNELS ISL54100CQZ ISL54101CQZ ISL54102CQZ NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020 ...
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... Thermal Resistance (Typical, Note 1) +0.3V MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 D Maximum Biased Junction Temperature . . . . . . . . . . . . . . . . +125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C Supply Voltage 3.3V, pixel rate = 165MHz COMMENT ...
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Electrical Specifications Specifications apply for V TMDS output load = 50Ω, TMDS output termination voltage V SYMBOL PARAMETER DIGITAL OUTPUT CHARACTERISTICS V Output HIGH Voltage 8mA Output LOW Voltage -8mA OL O POWER ...
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ISL54100 Pin Configuration 1 ADDR2 RX2-_B 5 RX2+ GND RXC-_A 10 RXC+ RXC-_B 13 RXC+ GND GND 18 GND 19 ...
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ISL54101 Pin Configuration 1 ADDR2 GND RXC-_A 10 RXC+ GND GND 18 GND 19 ...
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ISL54102 Pin Configuration 1 ADDR2 RX2-_B 5 RX2+ GND RXC-_A 10 RXC+ RXC-_B 13 RXC+ GND GND 18 GND 19 ...
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Pin Descriptions SYMBOL RX0-_A, RX0+_A, RX1-_A, RX1+_A, TMDS Inputs. Incoming TMDS data signals for Channel A. RX2-_A, RX2+_A RX0-_B, RX0+_B, RX1-_B, RX1+_B, TMDS Inputs. Incoming TMDS data signals for Channel B (ISL54100 and ISL54102 only). RX2-_B, RX2+_B RX0-_C, RX0+_C, RX1-_C, ...
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Register Listing ADDRESS REGISTER (DEFAULT VALUE) 0x00 Device ID (read only) 0x01 Channel Activity Detect (read only) 0x02 Channel Selection (0x0C) 9 ISL54100, ISL54101, ISL54102 BIT(S) FUNCTION NAME 3:0 Device Revision 1 = initial silicon second revision, etc. ...
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Register Listing (Continued) ADDRESS REGISTER (DEFAULT VALUE) 0x03 Input Control (0x12) Recommended default: 0x62 10 ISL54100, ISL54101, ISL54102 BIT(S) FUNCTION NAME 0 Tri-state Unselected 0: Normal Operation Clock Inputs 1: Termination of unselected TMDS clock inputs is tri-stated to save ...
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Register Listing (Continued) ADDRESS REGISTER (DEFAULT VALUE) 0x04 Termination Control (0x00) 0x05 Output Options (0x00) 0x06 Data Output Drive (0x00) 11 ISL54100, ISL54101, ISL54102 BIT(S) FUNCTION NAME 0 Data Termination A 0: Channel A TMDS Data inputs terminated into 50Ω ...
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Register Listing (Continued) ADDRESS REGISTER (DEFAULT VALUE) 0x07 Equalization 1 (0xCC) 0x08 Equalization 2 (0xCC) 0x09 Test Pattern Generator (0x00) 0x0A PRBS7 Error Counter Link 0 (read only) 0x0B PRBS7 Error Counter Link 1 (read only) 0x0C PRBS7 Error Counter ...
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Application Information The ISL54100, ISL54101, and ISL54102 are TMDS regenerators, locking to the incoming DVI or HDMI signal with triple Clock Data Recovery units (CDRs) and a Phase Locked Loop (PLL). The PLL generates a low jitter pixel clock from ...
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Power-down The chip can be placed in a Power-down mode when not in use to conserve power. Setting the Power-down bit (register 0x02 bit pulling the PD input pin high places the chip in a ...
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Typical Performance Setup A (Figure 4) was used to capture the TMDS eye diagrams shown in Figure 5 and Figure 6: CHROMA 2326 VIDEO PATTERN 15m DUAL-LINK GENERATOR @ DVI CABLE UXGA 60Hz FIGURE 5 FIGURE 6 FIGURE 4. TEST ...
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... N ISL5410x ISL5410xA Tx N Intersil recommends adding the Schottky circuit to all designs to reduce Rx current drain in systems using the original version and completely eliminate it in systems using the “A” version. PCB Layout Recommendations Because of the high speed of the TMDS signals, careful PCB layout is critical to maximize performance ...
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Failure to meet this requirement will increase reflections, shrinking the available eye. • Avoid vias for all 3 high speed TMDS pairs. Vias add inductance which causes a discontinuity in the characteristic ...
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ISL5410x Serial Communication Overview The ISL5410x uses a 2-wire serial bus for communication with its host. SCL is the Serial Clock line, driven by the host and SDA is the Serial Data line, which can be driven by all devices ...
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SCL SDA FIGURE 16. VALID DATA CHANGES ON THE SDA BUS START Command ISL5410x Serial Bus ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 (Repeat if desired) STOP Command S T Serial Bus ...
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START Command ISL5410x Serial Bus ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 START Command ISL5410x Serial Bus ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 (Repeat if desired) STOP Command S T Serial Bus Signals from A ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...