PCA9541D/01,118 NXP Semiconductors, PCA9541D/01,118 Datasheet - Page 20

• Manufacturer Part Number: PCA9541D/01,118
• Description: IC I2C 2:1 SELECTOR 16-SOIC
• Manufacturer: NXP Semiconductors

Specifications of PCA9541D/01,118

• Package / Case: 16-SOIC (3.9mm Width)
• Applications: 2-Channel I²C Multiplexer
• Interface: I²C, SMBus
• Voltage - Supply: 2.3 V ~ 5.5 V
• Mounting Type: Surface Mount
• Logic Family: PCA
• Propagation Delay Time: 0.3 ns
• Operating Supply Voltage: 2.3 V to 3.6 V
• Power Dissipation: 400 mW
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Output Current: 25 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-3615 - DEMO BOARD I2C
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-1849-2; 935273298118; PCA9541D/01-T

NXP Semiconductors
PCA9541_7
Product data sheet
Fig 11. System configuration
SDA
SCL
TRANSMITTER/
RECEIVER
MASTER
9.3 System configuration
9.4 Acknowledge
A device generating a message is a ‘transmitter’, a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see
The number of data bytes transferred between the START and the STOP conditions from
transmitter to receiver is not limited. Each byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,
whereas the master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of
each byte. Also a master must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter. The device that acknowledges has to
pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable
LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold
times must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
Fig 12. Acknowledgement on the I
RECEIVER
SLAVE
SCL from master
by transmitter
data output
by receiver
data output
TRANSMITTER/
RECEIVER
Rev. 07 — 2 July 2009
condition
START
SLAVE
2-to-1 I
S
Figure
2
C-bus master selector with interrupt logic and reset
2
C-bus
TRANSMITTER
1
11).
MASTER
2
TRANSMITTER/
RECEIVER
MASTER
acknowledgement
not acknowledge
SLAVE
clock pulse for
acknowledge
8
MULTIPLEXER
PCA9541
© NXP B.V. 2009. All rights reserved.
002aaa987
I
2
9
C-BUS
002aaa966
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