Z1601720ASG1868 Zilog, Z1601720ASG1868 Datasheet - Page 81
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Z1601720ASG1868
Manufacturer Part Number
Z1601720ASG1868
Description
IC PCMCIA INTERFACE 100-VQFP
Manufacturer
Zilog
Datasheets
1.Z1601720ASC1868.pdf
(138 pages)
2.Z1601720ASG1868.pdf
(134 pages)
3.Z1601720ASG1868.pdf
(138 pages)
Specifications of Z1601720ASG1868
Applications
*
Interface
*
Voltage - Supply
*
Package / Case
100-LQFP
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Part Number
Manufacturer
Quantity
Price
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EEPROM Register
Address: SELECT 2Bh
Name: Power Management Control Register
Type: Read/Write
1. When the En_Pads bit is set, access to the CCR Registers is disabled.
Programming Internal Registers
NOTES:
Bit Placement
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Table 53.
Bit Name
EN_8BIT_MODE
EN_MODEM_ALT
EN_CLK
EN_PADS
EN_TIMER
EN_PM_RDY
EN_EXT_PD
EN_EXPD_POL
1
Power Management control Register: Address 2Bh
Z86017/Z16017 PCMCIA Interface Solution
Description
When set to 1, this bit enables the 8-bit mode on the local
interface. When cleared, it enables the 16-bit interface.
When set to 1, this bit enables the alternate modem
functions/pins. When cleared, it disables modem functions.
When this bit is set to 1, all internal clocks are disabled
after loading from the serial EEPROM. When this bit is
cleared, all clocks are enabled.
When this bit is set to 1, the PCMCIA external pads are
powered-down, unless PCMCIA(*) PC_HCE1 and
PC_HCE2 are active. When this bit is cleared, all external
pads are enabled.
When this bit is set to 1, the power management timer is
enabled. The timer value is contained in Register 2A.
When this bit is cleared, the power management timer is
held reset and disabled.
When this bit is set to 1, the ZX6017 sets BUSY on the
PCMCIA interface when the host sets the power down bit
in CCR1.
When this bit is set to 1, the power management timer
activates the external power down signal EXTP_PWND.
When this bit is cleared, the external signal is not be
activated. See also Register 0Bh (Table 67).
When this bit is set to 1, the external power down signal
EXTP_PWND is active Low. When this bit is cleared,
EXTP_PWND is active High.
Reference Manual
RM001102-0901
67
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