Z1601720ASG1868 Zilog, Z1601720ASG1868 Datasheet - Page 19

• Manufacturer Part Number: Z1601720ASG1868
• Description: IC PCMCIA INTERFACE 100-VQFP
• Manufacturer: Zilog

Specifications of Z1601720ASG1868

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 100-LQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCMCIA Interface Overview
PCMCIA
Host
PC_BVD2/SPKR/DASP/DREQ
PC_BVD1/STSCHG/PDIAG
PC_RDY//BSY/IREQ/HINT
PC_WP/IOIS16/IOCS16
PC_HRESET/HRESET
Figure 2.
Serial Port Operation (SLAVE) Mode
When the ZX6017 is placed in serial port SLAVE mode (EE_Master
signal grounded on POR), the EEPROM sequencer is disabled and the
user must provide external hardware (microprocessor) with serial
interface to program CCRs and attribute memory. Additionally, if the
PC_WAIT/IOCHRDY
PC_INPACK/DREQ
PC_HCE1/HCS0
PC_HCE2/HCS1
PC_REG/DACK
PC_DATA 15:0
PC_ATA/HOE
PCMCIA Bus
PC_HA 10:0
PC_HIOW
PC_HIOR
PC_HWE
Serial Port Master Mode Control
EEPROM or
Z86017/Z16017 PCMCIA Interface Solution
Start/Range
Start/Range
Start/Range
Window 1
Window 2
Window 3
Z86017
Attribute
Memory
Control
Decoder
Decoder
Decoder
Decoder
A TA/IDE
Window
P
Local Peripheral Bus
ATA_DATA 15:0
ATA_HCS0
ATA_HCS1
ATA_HA0
ATA_HA1
ATA_HA2
ATA_HIOR
ATA_HIOW
ATA_MRD
ATA_MWR
ATA_IOCHRDY
ATA_IREQ
ATA_IOCS16
ATA_RESET
ATA_DREQ/BVD1
ATA_PDASP/EXTP_WP
ATA_PDIAG/ATA_BHE/RING_IN
ATA_DACK/BVD2
EXTP_PWDN
EXTP_AUDIO
EXTP_STSCHG/RES2
PC_MCLK_IN
POR
EE_CS
EE_SK
EE_DI
EE_MASTER
EE_DO
M_PINT
Product Specification
Chip Selects
Address Selects
Memory R/W
I/O R/W
Strobes
Strobes
GND ORG NC VCC
CS
EEPROM
CK DO DI
CLK
PS012002-1201
POR
Bus Interface
0.1 F
Peripheral
General
5