Z1601720ASG1868 Zilog, Z1601720ASG1868 Datasheet - Page 82

• Manufacturer Part Number: Z1601720ASG1868
• Description: IC PCMCIA INTERFACE 100-VQFP
• Manufacturer: Zilog

Specifications of Z1601720ASG1868

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 100-LQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

68
EEPROM Register
Name: ATA/IDE Dual Drive Control
Type: Read/Write
1. Read Back Values: Z86017 00010000b = 10h
EEPROM Register
Address: SELECT 2Ah
Name: Power Management Timer Count Value
Type: Read/Write
PS012002-1201
NOTES:
Bit Placement
Bit 7-0
Address: SELECT 28h
Bit Placement
Bit 0
Bit 1
Bit 7-2
Z16017 00100000b = 20h
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
Table 52.
Bit Name
TIMER_VAL
Bit Name
M_S_enable
Drive_select
Reserved
Power Management Timer Count Value: Address 2Ah
Description
Power management timer count value. The timer reset
during all PCMCIA activity. When the timer expires, it
powers down all noncritical signals. TIMER intervals
(sec.) = PC_MCLK (sec.) * 2(27) * timer_val. For
example: PC_MCLK (20 MHz, 50 ns) * 2(27) * 1 = 6.67
sec. Also see Register 2Ch (Table 56).
Description
this bit is set to 1, the Master/Slave function is enabled.
When it is set to 0, this function is disabled.
ATA/IDE bus. When set to 1, the ZX6017 drives the
ATA bus when the host writes a 1 into Bit 4 of the
“Drive/Head” task file register. Both primary and
secondary addresses are compared. If this bit is set to 0,
then the ZX6017 drives the bus if the host writes a 0 into
Bit 4 of the “Drive/Head” task fie register.
Unused
This bit enables the Master/Slave mode control. When
When programmed, this bit determines when to drive the
Programming Internal Registers
1