PI7C9X110BNBE Pericom Semiconductor, PI7C9X110BNBE Datasheet - Page 85

• Manufacturer Part Number: PI7C9X110BNBE
• Description: IC PCIE TO PCI REV BRG 160LFBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X110BNBE

• Applications: PCI-to-PCI Bridge
• Interface: I²C
• Voltage - Supply: 1.8 V
• Package / Case: 160-LBGA
• Mounting Type: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Rad Hardened: No
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Compliant

7.5.29 ARBITER ENABLE REGISTER – OFFSET 48h
Pericom Semiconductor – Confidential
BIT
23
24
26:25
27
28
29
30
31
FUNCTION
Fast Back-to-Back Capable
Master Data Parity Error
Detected
DEVSEL_L Timing
(medium decode)
Signaled Target Abort
Received Target Abort
Received Master Abort
Signaled System Error
Detected Parity Error
TYPE
RWC
RWC
RWC
RWC
RWC
RWC
RO
RO
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DESCRIPTION
This bit applies to forward bridge only.
1: Enable fast back-to-back transactions
Reset to 0 when reverse bridge or 1 when forward bridge with secondary bus
in PCI mode
Bit set if its Parity Error Enable bit is set and either of the conditions occurs
on the secondary:
REVERSE BRIDGE –
•
•
FORWARD BRIDGE –
•
•
•
Reset to 0
These bits apply to forward bridge only.
00: fast DEVSEL_L decoding
01: medium DEVSEL_L decoding
10: slow DEVSEL_L decoding
11: reserved
Reset to 00 when reverse bridge or 01 when forward bridge.
REVERSE BRIDGE –
This bit is set when PI7C9X110 completes a request using completer abort
status on the secondary
FORWARD BRIDGE –
This bit is set to indicate a target abort on the secondary
Reset to 0
REVERSE BRIDGE –
This bit is set when bridge receives a completion with completer abort
completion status on the secondary
FORWARD BRIDGE –
This bit is set when PI7C9X110 detects a target abort on the secondary
Reset to 0
REVERSE BRIDGE –
This bit is set when PI7C9X110 receives a completion with unsupported
request completion status on the secondary
FORWARD BRIDGE –
This bit is set when PI7C9X110 detects a master abort on the secondary
REVERSE BRIDGE –
This bit is set when PI7C9X110 sends an ERR_FATAL or
ERR_NON_FATAL message on the secondary
FORWARD BRIDGE –
This bit is set when PI7C9X110 asserts SERR_L on the secondary
Reset to 0
REVERSE BRIDGE –
This bit is set when poisoned TLP is detected on the secondary
FORWARD BRIDGE –
This bit is set when address or data parity error is detected on the secondary
Reset to 0
Receives a completion marked poisoned
Poisons a write request
Detected parity error when receiving data or Split Response for read
Observes P_PERR_L asserted when sending data or receiving Split
Response for write
Receives a Split Completion Message indicating data parity error
occurred for non-posted write
April 2010, Revision 3.0
PCIe-to-PCI Reversible Bridge
PI7C9X110