PC28F128J3D75B Numonyx - A DIVISION OF MICRON SEMICONDUCTOR PRODUCTS, INC., PC28F128J3D75B Datasheet - Page 24

IC FLASH 128MBIT 75NS 64EZBGA

PC28F128J3D75B

Manufacturer Part Number
PC28F128J3D75B
Description
IC FLASH 128MBIT 75NS 64EZBGA
Manufacturer
Numonyx - A DIVISION OF MICRON SEMICONDUCTOR PRODUCTS, INC.
Series
-r
Datasheet

Specifications of PC28F128J3D75B

Format - Memory
FLASH
Memory Type
FLASH
Memory Size
128M (16Mx8, 8Mx16)
Speed
75ns
Interface
Parallel
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
872768
872768TR
872768TR
PC28F128J3D75 872768
PC28F128J3D75B
PC28F128J3D75BTR

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PC28F128J3D75B
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Table 10: Read Operations (Sheet 2 of 2)
Notes:
1.
2.
3.
4.
5.
6.
Datasheet
24
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
#
CE
CE0, CE1, or CE2 that disables the device (see
256-Mb” on page 31
See AC Input/Output Reference Waveforms for the maximum allowable input slew rate.
OE# may be delayed up to t
“Chip Enable Truth Table for 32-, 64-, 128- and 256-Mb” on page 31
See
Equivalent Testing Load Circuit” on page 30
Sampled, not 100% tested.
For devices configured to standard word/byte read mode, R15 (t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
AVQV
ELQV
GLQV
PHQV
ELQX
GLQX
EHQZ
GHQZ
OH
ELFL/
FLQV/
FLQZ
EHEL
APA
GLQV
X
Sym
Figure 15, “AC Input/Output Reference Waveform” on page 30
low is defined as the first edge of CE0, CE1, or CE2 that enables the device. CE
t
t
ELFH
FHQV
Asynchronous Specifications V
Address to Output Delay
CE
OE# to Non-Array Output Delay
RP# High to Output Delay
CE
OE# to Output in Low Z
CE
OE# High to Output in High Z
Output Hold from Address, CE
Change, Whichever Occurs First
CE
BYTE# to Output Delay
BYTE# to Output in High Z
CEx High to CEx Low
Page Address Access Time
OE# to Array Output Delay
X
X
X
X
to Output Delay
to Output in Low Z
High to Output in High Z
Low to BYTE# High or Low
).
ELQV
Parameter
-t
GLQV
after the first edge of CE0, CE1, or CE2 that enables the device (see
X
, or OE#
Table 16, “Chip Enable Truth Table for 32-, 64-, 128- and
CC
= 2.7 V–3.6 V
for testing characteristics.
Numonyx™ Embedded Flash Memory (J3 v D, Monolithic)
Density
128 Mbit
256 Mbit
128 Mbit
256 Mbit
128 Mbit
256 Mbit
32 Mbit
64 Mbit
32 Mbit
64 Mbit
32 Mbit
64 Mbit
All
All
All
All
APA
(3)
) will equal R2 (t
and V
Min
0
0
0
0
CCQ
= 2.7 V–3.6 V
X
AVQV
and
Max
high is defined as the first edge of
150
180
210
210
75
75
75
95
75
75
75
95
25
25
15
10
25
25
1
1
) without impact on t
).
Figure 16, “Transient
(3)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
December 2007
Table 16,
ELQV
Notes
1,2,5
1,2,5
1,2,5
1,2,4
1,2,4
1,2,5
1,2,5
1,2,5
1,2,5
1,2,5
316577-06
5, 6
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
.

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