PC28F128J3D75D Numonyx - A DIVISION OF MICRON SEMICONDUCTOR PRODUCTS, INC., PC28F128J3D75D Datasheet - Page 31

• Manufacturer Part Number: PC28F128J3D75D
• Description: IC FLASH 128MBIT 75NS 64EZBGA
• Manufacturer: Numonyx - A DIVISION OF MICRON SEMICONDUCTOR PRODUCTS, INC.
• Series: -r

Specifications of PC28F128J3D75D

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 128M (16Mx8, 8Mx16)
• Speed: 75ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 872831; 872831TR; 872831TR; PC28F128J3D75 S L8QU; PC28F128J3D75D; PC28F128J3D75DTR

Numonyx™ Embedded Flash Memory (J3 v D, Monolithic)
8.0
Table 15: Bus Operations
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
Table 16: Chip Enable Truth Table for 32-, 64-, 128- and 256-Mb
December 2007
316577-06
Async., Status, Query and
Identifier Reads
Output Disable
Standby
Reset/Power-down
Command Writes
Array Writes
Note:
See
OE# and WE# should never be asserted simultaneously. If done so, OE# overrides WE#.
DQ refers to DQ[7:0} when BYTE# is low and DQ[15:0] if BYTE# is high.
Refer to DC characteristics. When V
X should be V
In default mode, STS is V
algorithm. It is V
suspend mode (with programming inactive), program suspend mode, or reset power-down mode.
See
operation
Array writes are either program or erase operations. /
For single-chip applications, CE2 and CE1 can be connected to
Table 16
Table 19, “Command Bus Operations” on page 35
(8)
CE2
V
V
V
V
V
V
V
V
Mode
IH
IH
IH
IH
IL
IL
IL
IL
Bus Interface
This section provides an overview of Bus operations. Basically, there are three
operations you can do with flash memory: Read, Program (Write), and Erase.The on-
chip Write State Machine (WSM) manages all erase and program algorithms. The
system CPU provides control of all in-system read, write, and erase operations through
the system bus. All bus cycles to or from the flash memory conform to standard
microprocessor bus cycles.
signal for different modes of operations.
The next few sections detail each of the basic flash operations and some of the
advanced features available on flash memory.
IL
for valid CE
or V
OH
(pulled up by an external pull up resistance ~= 10k) when the WSM is not busy, in block erase
IH
for the control pins and V
OL
x
when the WSM is executing internal block erase, program, or a lock-bit configuration
Configurations.
RP#
V
V
V
V
V
V
IH
IH
IH
IH
IH
IL
PEN
CE1
V
V
V
V
V
V
V
V
Enabled
Enabled
Enabled
Enabled
Disable
IH
IH
IH
IH
IL
IL
IL
IL
CE
≤
d
X
x
(1)
V
Table 15
PENLK
PENLK
OE#
, memory contents can be read but not altered.
V
V
V
V
X
X
or V
IL
IH
IH
IH
(2)
summarizes the necessary states of each control
PENH
WE#
for V
V
V
V
V
GND
X
X
IH
IH
IL
IL
(2)
PEN
.
for valid DIN (user commands) during a Write
. For outputs, X should be V
CE0
V
V
V
V
V
V
V
V
IH
IH
IH
IH
V
IL
IL
IL
IL
V
PENH
PEN
X
X
X
X
X
DQ
High Z
High Z
High Z
D
15:0
D
OUT
X
IN
(3)
OL
(Default
Mode)
High Z
High Z
High Z
High Z
High Z
or V
Disabled
Disabled
Disabled
Disabled
DEVICE
Enabled
Enabled
Enabled
Enabled
STS
V
IL
OH
.
Datasheet
Notes
4,6
6,7
8,5
31