LM5117PMH/NOPB National Semiconductor, LM5117PMH/NOPB Datasheet - Page 17

• Manufacturer Part Number: LM5117PMH/NOPB
• Description: IC BUCK CONTROLLER 20-TSSOP
• Manufacturer: National Semiconductor
• Series: -r

Specifications of LM5117PMH/NOPB

• Pwm Type: Current Mode
• Number Of Outputs: 1
• Frequency - Max: 530kHz
• Duty Cycle: 95%
• Voltage - Supply: 5.5 V ~ 65 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-TSSOP (0.173", 4.40mm Width) Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

HO and LO Drivers
The LM5117 contains high current NMOS drivers and an as-
sociated high-side level shifter to drive the external high-side
NMOS device. This high-side gate driver works in conjunction
with an external diode D
0.1μF or larger ceramic capacitor, connected with short traces
between the HB and SW pin, is recommended. During the off-
time of the high-side NMOS driver, the SW pin voltage is
approximately 0V and the C
the D
high-side NMOS device is forced off each cycle for 320ns to
ensure that C
The LO and HO outputs are controlled with an adaptive dead-
time methodology which insures that both outputs are never
enabled at the same time. When the controller commands HO
to be enabled, the adaptive dead-time logic first disables LO
and waits for the LO voltage to drop. HO is then enabled after
a small delay (LO Fall to HO Rise Delay). Similarly, the LO
turn-on is delayed until the HO voltage has discharged. LO is
then enabled after a small delay (HO Fall to LO Rise Delay).
This technique insures adequate dead-time for any size
NMOS device, especially when VCC is supplied by a higher
external voltage source. The adaptive dead-time circuitry
monitors the voltages of HO and LO outputs and insures the
dead-time between the HO and LO outputs. Adding a gate
resister, R
Care should be exercised in selecting an output NMOS device
with the appropriate threshold voltage, especially if VCC is
supplied by an external bias supply voltage below the VCC
regulation level. During startup at low input voltages, the low-
side NMOS device gate plateau voltage should be lower than
the VCC under-voltage lockout threshold. Otherwise, there
may be insufficient VCC voltage to completely enhance the
NMOS device as the VCC under-voltage lockout is released
during startup. If the high-side NMOS drive voltage is lower
than the high-side NMOS device gate plateau voltage during
startup, the regulator may not start or it may hang up mo-
mentarily in a high power dissipation state. This condition can
be addressed by selecting an NMOS device with a lower
threshold voltage. This situation can be avoided if the mini-
mum input voltage programmed by the UVLO resistor is
above the VCC regulation level.
Current Monitor
The LM5117 provides average output current information,
enabling various applications requiring monitoring or control
of the output current.
HB
. When operating with a high PWM duty cycle, the
GH
or R
HB
FIGURE 14. Current Monitor
is recharged.
GL
, may decrease the effective dead-time.
HB
, and bootstrap capacitor C
HB
is charged from VCC through
30143280
HB
. A
17
The average of CM output can be calculated by:
The current monitor output is only valid in continuous con-
duction operation. The current monitor has a limited band-
width of approximately one tenth of f
R
frequency below one tenth of f
ate sampling noise.
Maximum Duty Cycle
When operating with a high PWM duty cycle, the high-side
NMOS device is forced off each cycle for 320ns to ensure that
C
current in the low-side NMOS FET. This forced off-time limits
the maximum duty cycle of the controller. When designing a
regulator with high switching frequency and high duty cycle
requirements, a check should be made of the required maxi-
mum duty cycle against the graph shown in
actual maximum duty cycle varies with the switching frequen-
cy as follows:
Thermal Protection
Internal thermal shutdown circuitry is provided to protect the
controller in the event the maximum junction temperature is
exceeded. When activated, typically at 165°C, the controller
is forced into a low power shutdown mode, disabling the out-
put drivers and the VCC regulator. This feature is designed to
prevent overheating and destroying the device.
CM
HB
and C
is recharged and to allow time to sample and hold the
FIGURE 15. Maximum Duty Cycle vs Switching
CM
, on the output of current monitor with the cut off
Frequency
SW
is recommended to attenu-
SW
. Adding an R-C filter,
Figure
30143214
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15. The
(14)