AD9887AKS-140 Analog Devices Inc, AD9887AKS-140 Datasheet - Page 27

• Manufacturer Part Number: AD9887AKS-140
• Description: IC INTRFACE ANALOG/DVI 160-MQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9887AKS-140

• Rohs Status: RoHS non-compliant
• Applications: Graphic Cards, VGA Interfaces
• Interface: Analog and Digital
• Voltage - Supply: 3.15 V ~ 3.45 V
• Package / Case: 160-MQFP, 160-PQFP
• Mounting Type: Surface Mount

Hex
Address
12H
13H
14H
15H
16H
17H
18H
19H
1AH
Read and
Write or
Read Only
R/W
R/W
R/W
RO
R/W
R/W
R/W
R/W
R/W
Bits
7:0
7:0
7:0
7:5
7:2
7:0
7:0
7:0
7:0
Default
Value
0
00100000
10111***
******1*
00000000
00000000
00000000
11111111
0
0
0
1
0
0
0
0
0
0
1
0
Table IX. Control Register Map (continued)
Register
Name
Active
Interface
Sync
Separator
Threshold
Control Bits
Polarity Status
Control Bits 2
Pre-Coast
Post-Coast
Test Register
Test Register
Function
Bit 7—AIO: Active Interface Override. If set to Logic 1, the user
can select the active interface via Bit 6. If set to Logic 0, the active
interface is selected via Bit 3 in Register 11H.
Bit 6—AIS: Active Interface Select. Logic 0 selects the analog inter-
face as active. Logic 1 selects the digital interface as active. Note:
The indicated interface will be active only if Bit 7 is set to Logic 1
or if both interfaces are active (Bits 6 or 7 and 4 = Logic 1 in
Register 11H.)
Bit 5—Active Hsync Override. If set to Logic 1, the user can select
the Hsync to be used via Bit 4. If set to Logic 0, the active interface
is selected via Bit 2 in Register 11H.
Bit 4—Active Hsync Select. Logic 0 selects Hsync as the active
sync. Logic 1 selects Sync-on-Green as the active sync. Note: The
indicated Hsync will be used only if Bit 5 is set to Logic 1 or if
both syncs are active (Bits 6, 7 = Logic 1 in Register 11H.)
Bit 3—Active Vsync Override. If set to Logic 1, the user can select
the Vsync to be used via Bit 2. If set to Logic 0, the active interface
is selected via Bit 1 in Register 11H.
Bit 2—Active Vsync Select. Logic 0 selects Raw Vsync as the
output Vsync. Logic 1 selects Sync Separated Vsync as the output
Vsync. Note: The indicated Vsync will be used only if Bit 3 is set
to Logic 1.
Bit 1—Coast Select. Logic 0 selects the coast input pin to be used for
the PLL coast. Logic 1 selects Vsync to be used for the PLL coast.
Bit 0—PWRDN. Full Chip Power-Down, active low. (Logic 0 =
Full Chip Power-Down, Logic 1 = Normal.)
Sync Separator Threshold—Sets the number of clocks the sync
separator will count to before toggling high or low. This should be
set to some number greater than the maximum Hsync or equaliza-
tion pulsewidth.
Bit 4—Must be set to 1 for proper operation.
Bit 3—Must be set to 0 for proper operation.
Bit 2—Scan Enable. (Logic 0 = Not Enabled, Logic 1 = Enabled.)
Bit 1—Coast Polarity Override. (Logic 0 = Polarity determined by
chip, Logic 1 = Polarity set by Bit 6 in Register 0Fh.)
Bit 0—Hsync Polarity Override. (Logic 0 = Polarity determined by
chip, Logic 1 = Polarity set by Bit 7 in Register 0Fh.)
Bit 7—Hsync Input Polarity Status. (Logic 1 = Active High,
Logic 0 = Active Low.)
Bit 6—Vsync Output Polarity Status. (Logic 0 = Active High,
Logic 1 = Active Low.)
Bit 5—Coast Input Polarity Status. (Logic 1 = Active High,
Logic 0 = Active Low.)
Bits [7:3]—Sync-On-Green Slicer Threshold
Bit 1—Must be set to 0 for proper operation.
Sets the number of Hsyncs that coast goes active prior to Vsync.
Sets the number of Hsyncs that coast goes active following Vsync.
Must be set to default for proper operation.
Must be set to 01000001 for proper operation.
AD9887