PX1011A-EL1/G,551 NXP Semiconductors, PX1011A-EL1/G,551 Datasheet - Page 11
![IC PCI-EXPRESS X1 PHY 81-LFBGA](/photos/6/94/69420/568-81-lfga_sot643-1_sml.jpg)
PX1011A-EL1/G,551
Manufacturer Part Number
PX1011A-EL1/G,551
Description
IC PCI-EXPRESS X1 PHY 81-LFBGA
Manufacturer
NXP Semiconductors
Specifications of PX1011A-EL1/G,551
Applications
PCI Express MAX to PCI Express PHY
Interface
IEEE 1149.1
Voltage - Supply
1.2 V
Package / Case
81-LFBGA
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-3247
935279563551
PX1011A-EL1/G-S
935279563551
PX1011A-EL1/G-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PX1011A-EL1/G,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Philips Semiconductors
Table 13.
[1]
[2]
PX1011A_PX1012A_2
Product data sheet
PWRDWN[1:0]
00b
01b
10b
11b
TXIDLE = 0
TXIDLE = 1
Summary of power management state
8.6 Receiver detect
8.7 Loopback
Power management state
P0, normal operation
P0s, power saving state
P1, lower power state
illegal, PHY will enter P1
When the PHY is in the P1 state, it can be instructed to perform a receiver detection
operation to determine if there is a receiver at the other end of the link. Basic operation of
receiver detection is that the MAC requests the PHY to do a receiver detect sequence by
asserting RXDET_LOOPB. When the PHY has completed the receiver detect sequence,
it drives the RXSTATUS signals to the value of 011b if a receiver is present, and to 000b if
there is no receiver. Then the PHY will assert PHYSTATUS to indicate the completion of
receiver detect operation. The MAC uses the rising edge of PHYSTATUS to sample the
RXSTATUS signals and then de-asserts RXDET_LOOPB. A few cycles after the
RXDET_LOOPB de-asserts, the PHYSTATUS is also de-asserted.
The PHY supports an internal loopback from the PCI Express receiver to the transmitter
with the following characteristics.
The PHY retransmits each 10-bit data and control symbol exactly as received, without
applying scrambling or descrambling or disparity corrections, with the following rules:
Fig 5. Receiver detect - receiver present
•
•
RXDET_LOOPB
RXSTATUS2,
RXSTATUS1,
RXSTATUS0
If a received 10-bit symbol is determined to be an invalid 10-bit code (i.e., no legal
translation to a control or data value possible), the PHY still retransmits the symbol
exactly as it was received.
If a SKP ordered set retransmission requires adding a SKP symbol to accommodate
timing tolerance correction, any disparity can be chosen for the SKP symbol.
PHYSTATUS
PWRDWN1,
PWRDWN0
RXCLK
TXCLK
000b
10b
Rev. 02 — 18 May 2006
Transmitter
on
idle
idle
-
[1]
[2]
[2]
Receiver
on
idle
idle
-
011b
PX1011A/PX1012A
TX PLL
on
on
on
-
PCI Express stand-alone X1 PHY
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
RXCLK
on
on
on
-
RX PLL/CDR
on
on
off
-
002aac173
11 of 32
000b