px1011a NXP Semiconductors, px1011a Datasheet

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px1011a

Manufacturer Part Number
px1011a
Description
Px1011a/px1012a Pci Express Stand-alone X1 Phy
Manufacturer
NXP Semiconductors
Datasheet

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1. General description
2. Features
2.1 PCI Express interface
2.2 PHY/MAC interface
The PX1011A/PX1012A is a high-performance, low-power, single-lane PCI Express
electrical PHYsical layer (PHY) that handles the low level PCI Express protocol and
signaling. The PX1011A/1012A PCI Express PHY is compliant to the PCI Express Base
Specification, Rev. 1.0a , and Rev. 1.1 . The PX1011A/1012A includes features such as
clock and data recovery (CDR), data serialization and de-serialization, 8b/10b encoding,
analog buffers, elastic buffer and receiver detection, and provides superior performance to
the Media Access Control (MAC) layer devices.
The PX1011A/1012A is a 2.5 Gbit/s PCI Express PHY with 8-bit data PXPIPE interface.
Its PXPIPE interface is a superset of the PHY Interface for the PCI Express (PIPE)
specification, enhanced and adapted for off-chip applications with the introduction of a
source synchronous clock for transmit and receive data. The 8-bit data interface operates
at 250 MHz with SSTL_2 signaling. The SSTL_2 signaling is compatible with the I/O
interfaces available in FPGA products.
The PX1011A/1012A PCI Express PHY supports advanced power management
functions. The PX1011AI/PX1012AI is for the industrial temperature range ( 40 C to
+85 C).
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PX1011A/PX1012A
PCI Express stand-alone X1 PHY
Rev. 02 — 18 May 2006
Compliant to PCI Express Base Specification 1.1
Single PCI Express 2.5 Gbit/s lane
Data and clock recovery from serial stream
Serializer and De-serializer (SerDes)
Receiver detection
8b/10b coding and decoding, elastic buffer and word alignment
Supports loopback
Supports direct disparity control for use in transmitting compliance pattern
Supports lane polarity inversion
Low jitter and Bit Error Rate (BER)
Based on Intel PHY Interface for PCI Express architecture v1.0 (PIPE)
Adapted for off-chip with additional synchronous clock signals (PXPIPE)
8-bit parallel data interface for transmit and receive at 250 MHz
2.5 V SSTL_2 class I signaling
Product data sheet

Related parts for px1011a

px1011a Summary of contents

Page 1

... Media Access Control (MAC) layer devices. The PX1011A/1012A is a 2.5 Gbit/s PCI Express PHY with 8-bit data PXPIPE interface. Its PXPIPE interface is a superset of the PHY Interface for the PCI Express (PIPE) specifi ...

Page 2

... I/O and PVT analog supply voltage 1 for serializer analog supply voltage 2 for serializer reference clock frequency ambient temperature operating commercial industrial Rev. 02 — 18 May 2006 PX1011A/PX1012A PCI Express stand-alone X1 PHY Min Typ Max 3.0 3.3 3.6 2.3 2.5 2.7 1.2 1.25 1.3 1.15 1 ...

Page 3

... Ordering information Table 2. Ordering information Type number Solder process PX1011A-EL1 SnPb solder ball compound PX1011A-EL1/G Pb-free (SnAgCu solder ball compound) PX1011AI-EL1/G Pb-free (SnAgCu solder ball compound) PX1012A-EL1/G Pb-free (SnAgCu solder ball compound) PX1012AI-EL1/G Pb-free (SnAgCu solder ball compound) 5. Marking Table 3. Line A ...

Page 4

... Ln_TxData0 Ln_TxData1 8b/10b ENCODE PARALLEL TO SERIAL 250 MHz clock CLK GENERATOR TX I/O REFCLK I/O TX_P TX_N REFCLK_P REFCLK_N Rev. 02 — 18 May 2006 PX1011A/PX1012A PCI Express stand-alone X1 PHY PCI Express MAC RXDATA [ 7:0 ] RESET_N PCI Express PHY REGISTER 8 10b/8b DECODE ELASTIC BUFFER 10 K28.5 SERIAL DETECTION TO ...

Page 5

... V DD DDA2 DDA1 V TMS V DDD1 DDD1 TCK TRST_N V DDD3 TDI DDD2 TDO TXIDLE V SS RESET_N RXPOL TXCOMP Rev. 02 — 18 May 2006 PX1011A/PX1012A PCI Express stand-alone X1 PHY 002aac171 RXDATA1 RXDATAK RXCLK RXDATA2 RXDATA0 RXVALID SS DDD2 PVT V PHYSTATUS SS V ...

Page 6

... J4 input SSTL_2 J3 input SSTL_2 H6 input SSTL_2 J6 input SSTL_2 Rev. 02 — 18 May 2006 PX1011A/PX1012A PCI Express stand-alone X1 PHY Table 5 to Table 12. Note that input and Signaling Description PCIe I/O differential input receive pair with 50 on-chip termination PCIe I/O PCIe I/O differential output transmit pair with ...

Page 7

... V CMOS G3 input 3.3 V CMOS H3 output 3.3 V CMOS Rev. 02 — 18 May 2006 PX1011A/PX1012A PCI Express stand-alone X1 PHY Description indicates symbol lock and valid data on RX_DATA and RX_DATAK used to communicate completion of several PHY functions including power management state transitions and receiver detection indicates receiver detection of an electrical idle; ...

Page 8

... Clock and Data Recovery (CDR), data serialization and de-serialization, 8b/10b encoding, analog buffers, elastic buffer and receiver detection. The PXPIPE interface between the MAC and PX1011A/1012A is a superset of the PHY Interface for the PCI Express (PIPE) specification. The following feature have been added: • ...

Page 9

... The PLL has a sufficiently high bandwidth to handle a 100 MHz reference clock with a 30 kHz to 33 kHz spread spectrum. 8.3 Clocking There are three clock signals used by the PX1011A/1012A: • REFCLK is a 100 MHz external reference clock that the PHY uses to generate the 250 MHz data clock and the internal bit rate clock ...

Page 10

... L1.idle state of the Link Training and Status State Machine (LTSSM). • P2 state: PHY will enter P1 instead. PX1011A_PX1012A_2 Product data sheet RXCLK Rev. 02 — 18 May 2006 PX1011A/PX1012A PCI Express stand-alone X1 PHY 100 MHz 250 MHz © Koninklijke Philips Electronics N.V. 2006. All rights reserved. 002aac172 ...

Page 11

... SKP symbol. PX1011A_PX1012A_2 Product data sheet Transmitter [1] on [2] idle [2] idle - TXCLK 10b RXCLK 000b Rev. 02 — 18 May 2006 PX1011A/PX1012A PCI Express stand-alone X1 PHY Receiver TX PLL RXCLK idle on on idle 011b © ...

Page 12

... Product data sheet Figure 6 shows example timing for beginning loopback. In this TXCLK Tx-m Tx-n RXCLK Rx-c Rx-d TX_P, TX_N Figure 7 shows an example of switching from loopback mode to Rev. 02 — 18 May 2006 PX1011A/PX1012A PCI Express stand-alone X1 PHY Tx-o Tx-p Tx-q Rx-e Rx-f Rx-g Tx-m Tx-n Rx-e © Koninklijke Philips Electronics N.V. 2006. All rights reserved. 002aac174 ...

Page 13

... Looped back RX data Figure 8 shows an example of timing for entering electrical idle. ScZero COM active (ends with Electrical Idle ordered-set) Rev. 02 — 18 May 2006 PX1011A/PX1012A PCI Express stand-alone X1 PHY Junk Junk IDL © Koninklijke Philips Electronics N.V. 2006. All rights reserved. 001aac785 002aac175 ...

Page 14

... PHY inserted a SKP symbol in the data stream. shows a sequence where the PHY removed a SKP symbol from a SKP RXCLK active COM RXVALID 000b 001b Rev. 02 — 18 May 2006 PX1011A/PX1012A PCI Express stand-alone X1 PHY Function description normal operation transmitter in idle loopback mode illegal illegal transmitter in idle ...

Page 15

... Elastic buffer underflow 4. Disparity error PX1011A_PX1012A_2 Product data sheet RXCLK active COM RXVALID 000b 010b Function table PXPIPE status interface signals Rev. 02 — 18 May 2006 PX1011A/PX1012A PCI Express stand-alone X1 PHY SKP active 000b Output pin RXSTATUS2 RXSTATUS1 RXSTATUS0 ...

Page 16

... RXCLK Rx-a Rx-b RXVALID 000b the receiver detected a disparity error on Rx-c data byte, and indicates this with RXCLK Rx-a Rx-b RXVALID 000b Figure Rev. 02 — 18 May 2006 PX1011A/PX1012A PCI Express stand-alone X1 PHY EDB Rx-d Rx-e 100b 000b Rx-c Rx-d Rx-e 111b 000b 13, the PHY is receiving a repeating set of © Koninklijke Philips Electronics N.V. 2006. All rights reserved. ...

Page 17

... Product data sheet RXCLK Rx-a Rx-b RXVALID 000b RXCLK Rx-a Rx-b RXVALID 000b RXCLK D21.5 D21.5 RXVALID RXPOL Rev. 02 — 18 May 2006 PX1011A/PX1012A PCI Express stand-alone X1 PHY Rx-c EDB Rx-d 110b 000b Rx-c Rx-e Rx-f 101b 000b D10.2 D10.2 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. 001aac782 001aac783 001aac786 ...

Page 18

... TRST_N to V PX1011A_PX1012A_2 Product data sheet TXCLK data K28.5 TXCOMP valid data . SS Rev. 02 — 18 May 2006 PX1011A/PX1012A PCI Express stand-alone X1 PHY K28.5 K28.5 K28.5 byte transmitted with negative disparity K28.5 K28.5 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. 002aac177 ...

Page 19

... Thermal characteristics Parameter thermal resistance from junction to ambient thermal resistance from junction to case Rev. 02 — 18 May 2006 PX1011A/PX1012A PCI Express stand-alone X1 PHY Conditions Min for JTAG I/O 0.5 for SSTL_2 I/O 0.5 for core 0.5 for high-speed 0 ...

Page 20

... IL(se)REFCLK t CDR lock time (reference loop) lock(CDR)(ref) t CDR lock time (data loop) lock(CDR)(data) t receiver latency RX_latency PX1011A_PX1012A_2 Product data sheet PX1011A/PX1012A Conditions for JTAG I/O for SSTL_2 I/O for core for high-speed serial I/O and PVT for serializer for serializer for I/O for SSTL_2; ...

Page 21

... TX_latency t P0s state exit latency P0s_exit_latency t P1 state exit latency P1_exit_latency t RESET_N HIGH to PHYSTATUS LOW time RESET-PHYSTATUS PX1011A_PX1012A_2 Product data sheet PX1011A/PX1012A …continued Conditions 1 clock cycle Rev. 02 — 18 May 2006 PCI Express stand-alone X1 PHY Min Typ Max Unit 399.88 400 400 ...

Page 22

... 1. 1. see Figure 17 see Figure 17 see Figure 17 see Figure 17 TXCLK PXPIPE INPUT t su(TX)(PXPIPE) RXCLK PXPIPE OUTPUT Rev. 02 — 18 May 2006 PX1011A/PX1012A PCI Express stand-alone X1 PHY Min Typ Max 249.925 250 250.075 249.925 250 250.075 [1] - 1. 0.68 1. ...

Page 23

... PX1011A_PX1012A_2 Product data sheet 0.6 0.5 0.4 signal (V) 0.3 0.2 0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.2 0.1 0 0.1 0 nominal V amb DD 0.6 0.5 differential 0.4 signal (V) 0.3 0.2 0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.2 0.1 0 0.1 0 nominal V amb DD Rev. 02 — 18 May 2006 PX1011A/PX1012A PCI Express stand-alone X1 PHY 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 unit intervals 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 unit intervals © Koninklijke Philips Electronics N.V. 2006. All rights reserved. 001aac789 1.1 1.2 001aac790 1.1 1 ...

Page 24

... 9.1 9.1 0.8 6.4 6.4 0.15 8.9 8.9 REFERENCES JEDEC JEITA MO-205 - - - Rev. 02 — 18 May 2006 PX1011A/PX1012A PCI Express stand-alone X1 PHY detail 0.08 0.12 0.1 EUROPEAN PROJECTION © Koninklijke Philips Electronics N.V. 2006. All rights reserved. SOT643-1 ISSUE DATE ...

Page 25

... Pb-free process - package peak reflow temperatures (from J-STD-020C July 2004) 3 Volume mm < 350 260 260 250 Rev. 02 — 18 May 2006 PX1011A/PX1012A PCI Express stand-alone X1 PHY 3 < 350 Volume mm 225 225 Volume mm 350 to ...

Page 26

... Suitability of surface mount IC packages for wave and reflow soldering methods [1] [3] , LBGA, LFBGA, SQFP, [3] , TFBGA, VFBGA, XSON , SO, SOJ [8] [9] [8] , PMFP , WQCCN..L Rev. 02 — 18 May 2006 PX1011A/PX1012A PCI Express stand-alone X1 PHY Soldering method Wave Reflow not suitable suitable [4] not suitable suitable suitable suitable [5][6] ...

Page 27

... Phase-Locked Loop PHY Interface for the PCI Express Process Voltage Temperature Serial to Parallel Serializer and De-serializer SKiP Stub Series Terminated Logic for 2.5 Volts Rev. 02 — 18 May 2006 PX1011A/PX1012A PCI Express stand-alone X1 PHY © Koninklijke Philips Electronics N.V. 2006. All rights reserved ...

Page 28

... Min and Max values for V – added condition “operating” for T – added industrial temperature range • Table 2 “Ordering PX1012A-EL1/G; added industrial temperature range Type numbers PX1011AI-EL1 and PX1012AI-EL1; added column “Soldering compound” • Figure 1 “Block diagram” • ...

Page 29

... PX1011A-EL1 interface between the MAC and – (new) 3rd paragraph added – removed “( 1 configuration)” from last paragraph • ...

Page 30

... OL(SSTL2) IH(SSTL2) Preliminary data sheet Rev. 02 — 18 May 2006 PX1011A/PX1012A PCI Express stand-alone X1 PHY Change notice Supersedes - PX1011A-EL1_1 interface”: deleted sentence 2 of 3rd paragraph; added modified (appended “I/O”) changed from “V , supply voltage for DD4 DD4 amb DDD2 ...

Page 31

... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. Rev. 02 — 18 May 2006 PX1011A/PX1012A PCI Express stand-alone X1 PHY © Koninklijke Philips Electronics N.V. 2006. All rights reserved ...

Page 32

... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © Koninklijke Philips Electronics N.V. 2006. For more information, please visit: http://www.semiconductors.philips.com. For sales office addresses, email to: sales.addresses@www.semiconductors.philips.com. Document identifier: PX1011A_PX1012A_2 All rights reserved. Date of release: 18 May 2006 ...

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