px1011a NXP Semiconductors, px1011a Datasheet - Page 15

• Manufacturer Part Number: px1011a
• Description: Px1011a/px1012a Pci Express Stand-alone X1 Phy
• Manufacturer: NXP Semiconductors

Philips Semiconductors
PX1011A_PX1012A_2
Product data sheet
8.10 Error detection
The PHY is responsible for detecting receive errors of several types. These errors are
signaled to the MAC layer using the receiver status signals RXSTATUS.
Table 15.
Because of higher level error detection mechanisms (like CRC) built into the data link layer
of PCI Express, there is no need to specifically identify symbols with errors. However,
timing information about when the error occurred in the data stream is important. When a
receive error occurs, the appropriate error code is asserted for one clock cycle at the point
closest to where the error actually occurred.
There are four error conditions that can be encoded on the RXSTATUS signals. If more
than one error should happen to occur on a received byte, the errors are signaled with the
priority shown below.
Operating mode
Received data OK
One SKP added
One SKP removed
Receiver detected
8b/10b decode error
Elastic buffer overflow
Elastic buffer underflow
Receive disparity error
1. 8b/10b decode error
2. Elastic buffer overflow
3. Elastic buffer underflow
4. Disparity error
Fig 10. Clock correction - remove a SKP
RXSTATUS2,
RXSTATUS1,
RXSTATUS0
RXDATA[7:0]
RXVALID
RXCLK
Function table PXPIPE status interface signals
active
000b
Rev. 02 — 18 May 2006
COM
010b
000b
SKP
Output pin
RXSTATUS2 RXSTATUS1 RXSTATUS0
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PX1011A/PX1012A
PCI Express stand-alone X1 PHY
active
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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