MC33394DH Freescale Semiconductor, MC33394DH Datasheet - Page 22

• Manufacturer Part Number: MC33394DH
• Description: IC POWER SUPPLY MULT-OUT 44-HSOP
• Manufacturer: Freescale Semiconductor

Specifications of MC33394DH

• Applications: Motorola MPC55x, MPC56x Microprocessors
• Interface: SPI Serial
• Voltage - Supply: 4 V ~ 26.5 V
• Package / Case: 44-BSOP (0.433", 11.00mm Width) Exposed Pad
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

33394 SPI Registers:
Serial Output Data/Status
Bit Definitions:
Bit 15 to 8 = 0
Bit Definitions:
Bit 7 — VSEN–T: – Will be set (1), if a thermal limit occurred since last SPI data transfer
Bit 6 — VREF3–T: – Will be set (1), if a thermal limit occurred since last SPI data transfer
Bit 5 — VREF2–T: – Will be set (1), if a thermal limit occurred since last SPI data transfer
Bit 4 — VREF1–T: – Will be set (1), if a thermal limit occurred since last SPI data transfer
Bit 3 — VSEN–I: – Will be set (1), if a current limit condition exists
Bit 2 — VREF3–I: – Will be set (1), if a current limit condition exists
Bit 1 — VREF2–I: – Will be set (1), if a current limit condition exists
Bit 0 — VREF1–I: – Will be set (1), if a current limit condition exists
NOTES: # individual thermal limit latch will clear on the trailing edge of the SPI CS signal
4.16. CAN Transceiver
’recessive’ bits. When the digital input (CANTXD) is a logic ”0”
(negated level, dominant bit), CANH goes to +3.5 V (nominal)
and CANL goes to +1.5 V (nominal). The digital output will also
be negated. When the digital input is logic ”1” (asserted level,
recessive bit), CANH and CANL are set to +2.5 V (nominal).
The corresponding digital output is also asserted.
4.16.1. CAN Network Topology
CANH and CANL outputs. The majority of the time, the module
4.16.2. CAN Transceiver Functional Description
10.
The transceiver has wake up capability controlled by the state
of the SPI bit WKUP. This allows 33394 to enter a low power
mode and be awakened by CAN bus activity. When activity is
22
Default Value
Bit
Name
Default Value
Bit
Name
The CAN protocol is defined in terms of ’dominant’ and
There are two 120
A block diagram of the CAN transceiver is shown in Figure
A summary of the network topology is shown in Figure 9.
CANH
CANL
VSEN–T
15
(only two), terminations between the
0
0
7
*Optional
PCM
120
W
Freescale Semiconductor, Inc.
VREF3–T
For More Information On This Product,
14
0
0
6
Common Mode Choke
Figure 8. SPI Output Data/ Status Register
Figure 9. CAN Load Characteristics
2.2 mH
Go to: www.freescale.com
VREF2–T
13
0
0
5
33394
VREF1–T
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
470 pF*
470 pF*
12
0
0
4
controller will contain one of the terminations. The other
termination should be as close to the other ”end” of the CAN
Bus as possible. The termination provides a total of 60
differential resistive impedance for generation of the voltage
difference between CANH and CANL. Current flows out of
CANH, through the termination, and then through CANL and
back to ground. The CAN bus is not defined in terms of the bus
capacitance. A filter capacitor of 220 pF to 470 pF may be
required. The maximum capacitive load on the CAN bus is
then 15 nF (not a lumped capacitance but distributed through
the network cabling). Refer to Figure 9.
sensed on the CAN bus pins, the 33394 will perform a power
up sequence and will provide the microprocessor with
indication (WAKEUP pin high) that wake up occurred from a
CAN message. The 33394 may be placed back in low
quiescent mode by pulling the /SLEEP pin from high to low.
Max : 31 Remotes
VSEN–I
11
0
0
3
470 pF*
470 pF*
VREF3–I
10
0
0
2
Vehicle Term.
120
VREF2–I
W
0
9
0
1
VREF1–I
0 (LSB)
0
8
0