ADG715BRUZ Analog Devices Inc, ADG715BRUZ Datasheet
ADG715BRUZ
Specifications of ADG715BRUZ
Available stocks
Related parts for ADG715BRUZ
ADG715BRUZ Summary of contents
Page 1
FEATURES ADG714 SPI™/QSPI™/MICROWIRE™-Compatible Interface 2 ADG715 I C™-Compatible Interface 2 5.5 V Single Supply 2.5 V Dual Supply 2.5 On Resistance 0.6 On Resistance Flatness 100 pA Leakage Currents Octal SPST Power-On Reset Fast Switching Times TTL/CMOS-Compatible ...
Page 2
ADG714/ADG715–SPECIFICATIONS Parameter ANALOG SWITCH Analog Signal Range On Resistance ( Resistance Match Between Channels (∆R On Resistance Flatness (R ) FLAT(ON) LEAKAGE CURRENTS Source OFF Leakage I (OFF) S Drain OFF Leakage I (OFF) D Channel ON ...
Page 3
SPECIFICATIONS (V DD Parameter ANALOG SWITCH Analog Signal Range On Resistance ( Resistance Match Between Channels (∆R On Resistance Flatness (R ) FLAT(ON) LEAKAGE CURRENTS Source OFF Leakage I (OFF) S Drain OFF Leakage I (OFF) ...
Page 4
ADG714/ADG715–SPECIFICATIONS DUAL SUPPLY (V = +2 Parameter ANALOG SWITCH Analog Signal Range On Resistance ( Resistance Match Between Channels (∆R On Resistance Flatness (R ) FLAT(ON) LEAKAGE CURRENTS Source OFF Leakage I (OFF) ...
Page 5
ADG714 TIMING CHARACTERISTICS Parameter Limit MIN f 30 SCLK 4 ...
Page 6
ADG714/ADG715 ADG715 TIMING CHARACTERISTICS Parameter Limit MIN MAX f 400 SCL 100 0 0 0.6 ...
Page 7
ABSOLUTE MAXIMUM RATINGS (T = 25°C unless otherwise noted ...
Page 8
ADG714/ADG715 Pin No. Mnemonic Description 1 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. These devices can accommodate serial input rates MHz. 2 ...
Page 9
V Most positive power supply potential Most negative power supply in a dual supply SS application. In single supply applications, this should be tied to ground. I Positive Supply Current DD I Negative Supply Current SS GND Ground ...
Page 10
ADG714/ADG715 –Typical Performance Characteristics DRAIN OR SOURCE VOLTAGE – ...
Page 11
(ON (OFF) I (OFF –0.02 –0.04 0 0.5 1.0 1.5 VOLTAGE – V TPC 7. Leakage Currents as a Function of V 0.04 0. (OFF) S ...
Page 12
ADG714/ADG715 –40 –50 –60 –70 –80 –90 –100 30k 100k 1M FREQUENCY – Hz TPC 13. Crosstalk vs. Frequency +2. –2.5V SS –5 –10 –15 –20 –3 –2 ...
Page 13
The 2-wire serial bus protocol operates as follows: 1. The master initiates data transfer by establishing a START condition, which is when a high-to-low transition on the SDA line occurs while SCL is high. The following byte is the address ...
Page 14
ADG714/ADG715 APPLICATIONS Multiple Devices On One Bus Figure 6 shows four ADG715 devices on the same serial bus. Each has a different slave address since the state of their A0 and A1 pins is different. This allows each switch to ...
Page 15
SPI bus. Figure 8 illustrates the ADG739 and mul- tiple ADG714s in such a typical configuration. All devices receive the same serial clock and serial data, but only one device will receive the SYNC signal at any ...
Page 16
ADG714/ADG715 24-Lead Thin Shrink Small Outline Package [TSSOP] PIN 1 0.15 0.05 Revision History Location 11/02—Data Sheet changed from REV REV. B. Edits to FEATURES . . . . . . . . . . . . . ...