ADG431BRZ Analog Devices Inc, ADG431BRZ Datasheet - Page 6

• Manufacturer Part Number: ADG431BRZ
• Description: IC SWITCH QUAD SPST 16SOIC
• Manufacturer: Analog Devices Inc
• Series: LC²MOSr
• Type: Analog Switchr

Specifications of ADG431BRZ

• Function: Switch
• Circuit: 4 x SPST - NO
• On-state Resistance: 24 Ohm
• Voltage Supply Source: Single Supply
• Voltage - Supply, Single/dual (±): 5V, 12V
• Current - Supply: 0.1µA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (0.154", 3.90mm Width)
• Analog Switch Type: SPST
• No. Of Channels: 4
• On State Resistance Max: 24ohm
• Turn Off Time: 60ns
• Turn On Time: 90ns
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Multiplexer Configuration: Quad SPST
• Number Of Inputs: 4
• Number Of Outputs: 4
• Number Of Channels: 4
• Analog Switch On Resistance: 42@10.8VOhm
• Analog Switch Turn On Time: 165ns
• Analog Switch Turn Off Time: 60ns
• Package Type: SOIC N
• Power Supply Requirement: Single/Dual
• Single Supply Voltage (min): 5V
• Single Supply Voltage (typ): 12V
• Single Supply Voltage (max): 25V
• Dual Supply Voltage (min): ±5V
• Dual Supply Voltage (typ): ±15V
• Dual Supply Voltage (max): ±22V
• Power Dissipation: 600mW
• Supply Current: 0.0001@±16.5VmA
• Mounting: Surface Mount
• Pin Count: 16
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADG431/ADG432/ADG433
TRENCH ISOLATION
In the ADG431A, ADG432A and ADG433A, an insulating
oxide layer (trench) is placed between the NMOS and PMOS
transistors of each CMOS switch. Parasitic junctions, which
occur between the transistors in junction isolated switches, are
eliminated, the result being a completely latch-up proof switch.
In junction isolation, the N and P wells of the PMOS and NMOS
transistors from a diode that is reverse-biased under normal
operation. However, during overvoltage conditions, this diode
becomes forward biased. A silicon-controlled rectifier (SCR)
type circuit is formed by the two transistors causing a significant
amplification of the current which, in turn, leads to latch up.
With trench isolation, this diode is removed, the result being a
latch-up proof switch.
110
100
120
100
90
80
70
60
80
60
40
100
100
1k
1k
FREQUENCY – Hz
FREQUENCY – Hz
10k
10k
100k
100k
V
V
V
V
V
V
DD
SS
L
1M
DD
SS
L
1M
= +5V
= –15V
= +5V
= +15V
= –15V
= +15V
10M
10M
APPLICATION
Figure 2 illustrates a precise, fast sample-and-hold circuit.
An AD845 is used as the input buffer while the output opera-
tional amplifier is an AD711. During the track mode, SW1 is
closed and the output V
the hold mode, SW1 is opened and the signal is held by the
hold capacitor C
Due to switch and capacitor leakage, the voltage on the hold
capacitor will decrease with time. The ADG431/ADG432/
ADG433 minimizes this droop due to its low leakage specifica-
tions. The droop rate is further minimized by the use of a
polystyrene hold capacitor. The droop rate for the circuit
shown is typically 30 µV/µs.
A second switch SW2, which operates in parallel with SW1, is
included in this circuit to reduce pedestal error. Since both
switches will be at the same potential, they will have a differen-
tial effect on the op amp AD711 which will minimize charge
injection effects. Pedestal error is also reduced by the compensa-
tion network R
the hold time glitch while optimizing the acquisition time. Using
the illustrated op amps and component values, the pedestal error
has a maximum value of 5 mV over the ± 10 V input range. Both
the acquisition and settling times are 850 ns.
V
IN
T
R
E
N
C
H
AD845
+15V
–15V
V
P
N
S
+
–
C
and C
P-CHANNEL
H
.
V
G
S
S
C
+15V
SUBSTRATE (BACKGATE)
SW2
SW1
. This compensation network also reduces
BURIED OXIDE LAYER
OUT
ADG431
ADG432
ADG433
V
P
D
+
–15V
+5V
follows the input signal V
T
R
E
N
C
H
D
D
75
V
N
P
R
S
–
+
C
2200pF
2200pF
N-CHANNEL
C
1000pF
C
C
V
H
G
AD711
+15V
–15V
V
N
D
+
IN
T
R
E
N
C
H
. In
V
OUT