EVAL-ADF7023-JDB1Z Analog Devices Inc, EVAL-ADF7023-JDB1Z Datasheet - Page 93

• Manufacturer Part Number: EVAL-ADF7023-JDB1Z
• Description: BOARD EVAL ADF7023-JDB1Z
• Manufacturer: Analog Devices Inc
• Series: -r
• Type: Transceiverr

Specifications of EVAL-ADF7023-JDB1Z

• Frequency: 902MHz ~ 958MHz
• Kit Application Type: Wireless Connectivity
• Application Sub Type: RF Transceiver
• Features: Operating At RF Band 902MHz To 958MHz, PC Interface And Control
• Silicon Manufacturer: Analog Devices
• Silicon Core Number: ADF7023
• Kit Contents: Board, Manual
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: ADF7023

Table 110. 0x328: ADC_READBACK_LOW
Bit
[7:6]
[5:0]
Table 111. 0x32D: BATTERY_MONITOR_THRESHOLD_VOLTAGE
Bit
[7:5]
[4:0]
Table 112. 0x32E: EXT_UC_CLK_DIVIDE
Bit
[7:4]
[3:0]
Table 113. 0x32F: AGC_CLK_DIVIDE
Bit
[7:0]
Table 114. 0x336: INTERRUPT_SOURCE_0
Bit
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
Table 115. 0x337: INTERRUPT_SOURCE_1
Bit
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
Name
BATTERY_ALARM
CMD_READY
Unused
WUC_TIMEOUT
Unused
Unused
SPI_READY
CMD_FINISHED
Name
ADC_READBACK[1:0]
Reserved
Name
Reserved
BATTMON_VOLTAGE
Name
Reserved
EXT_UC_CLK_DIVIDE
Name
AGC_CLOCK_DIVIDE
Name
INTERRUPT_NUM_WAKEUPS
INTERRUPT_SWM_RSSI_DET
INTERRUPT_AES_DONE
INTERRUPT_TX_EOF
INTERRUPT_ADDRESS_MATCH
INTERRUPT_CRC_CORRECT
INTERRUPT_SYNC_DETECT
INTERRUPT_PREAMBLE_DETECT
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Reset
0
0
Reset
0
0
Reset
0
4
Reset
40
Reset
0
0
0
0
0
0
0
0
Rev. 0 | Page 93 of 100
Description
Battery voltage dropped below the user-set threshold value
Communications processor ready to accept a new command
Wake-up timer has timed out
SPI ready for access
Command has finished
Description
ADC readback of LSBs
Description
The battery monitor threshold voltage sets the alarm level for the battery
monitor. The alarm is raised by the interrupt. Battery monitor trip voltage,
V
Description
Optional output clock frequency on XOSC32KP_GP5_ATB1.
Output frequency = XTAL/EXT_UC_CLK_DIVIDE. To disable,
set EXT_UC_CLK_DIVIDE = 0.
Description
AGC clock divider for 2FSK/GFSK/MSK/GMSK mode. The AGC rate is
(26 MHz/(16 × AGC_CLK_DIVIDE)).
Description
Asserted when the number of WUC wake-ups
(NUMBER_OF_WAKEUPS[15:0]) has reached the threshold
(NUMBER_OF_WAKEUPS_IRQ_THRESHOLD[15:0])
Asserted when the measured RSSI during smart wake mode has
exceeded the RSSI threshold value (SWM_RSSI_THRESH, Address 0x108)
Asserted when an AES encryption or decryption command is complete;
available only when the AES firmware module has been loaded to the
ADF7023-J program RAM
Asserted when a packet has finished transmitting (packet mode only)
Asserted when a received packet has a valid address match (packet
mode only)
Asserted when a received packet has the correct CRC (packet mode only)
Asserted when a qualified sync word has been detected in the received
packet
Asserted when a qualified preamble has been detected in the received
packet
TRIP
= 1.7 V + 62 mV × BATTMON_VOLTAGE.
ADF7023-J