SI4704-D60-GM Silicon Laboratories Inc, SI4704-D60-GM Datasheet - Page 21

• Manufacturer Part Number: SI4704-D60-GM
• Description: IC FM RADIO TUNER 20-QFN
• Manufacturer: Silicon Laboratories Inc
• Series: -r

Specifications of SI4704-D60-GM

• Frequency: 64MHz ~ 108MHz
• Sensitivity: -
• Data Rate - Maximum: -
• Modulation Or Protocol: FM
• Applications: General Purpose
• Current - Receiving: 10.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: -
• Antenna Connector: PCB, Surface Mount
• Features: RSSI Equipped
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-UFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.2. Operating Modes
The Si4704/05-D60 operates in either an FM receive or
audio AUXIN ADC mode. In FM mode, radio signals are
received on FMI and processed by the FM front-end
circuitry. In audio AUXIN ADC mode, stereo audio
signals on LIN/RIN are sampled, converted to digital,
filtered, and decimated to 32, 44.1, or 48 kHz for the I
digital audio interface. In addition to the receiver mode,
there is a clocking mode to choose to clock the
Si4704/05-D60 from a reference clock or crystal. On the
Si4704/05-D60, there is an audio output mode to
choose between an analog and/or digital audio output.
In the analog audio output mode, ROUT and LOUT are
used for the audio output pins. In the digital audio mode,
DOUT, DFS, and DCLK pins are used. Concurrent
analog/digital audio output mode is also available
requiring all five pins.
4.3. FM Receiver
The Si4704/05-D60 FM receiver is based on the proven
Si4700/01 FM tuner. The receiver uses a digital low-IF
architecture
components and factory adjustments. The Si4704/05-
D60 integrates a low noise amplifier (LNA) supporting
the worldwide FM broadcast band (64 to 108 MHz). An
AGC circuit controls the gain of the LNA to optimize
sensitivity and rejection of strong interferers. An image-
reject mixer downconverts the RF signal to low-IF. The
quadrature mixer output is amplified, filtered, and
digitized
converters (ADCs). This advanced architecture allows
the Si4704/05-D60 to perform channel selection, FM
demodulation, and stereo audio processing to achieve
superior performance compared to traditional analog
architectures.
4.4. Stereo Audio AUXIN ADC
The Si4704/05-D60 stereo audio AUXIN ADC can be
multiplexed between low-IF input for radio operation
and analog audio input for high fidelity data conversion
at 32, 44.1, or 48 kHz sample rate. When operated in
ADC-mode, the Si4704/05-D60 supports I
audio output only (no analog output) while enabling the
analog inputs and the stereo ADC.
4.5. Digital Audio Interface
The digital audio interface operates in slave mode and
supports a variety of MSB-first audio data formats
including I
three pins: digital data input (DIN), digital frame
synchronization
synchronization input clock (DCLK). The Si4704/05-D60
supports a number of industry-standard sampling rates
2
S and left-justified modes. The interface has
with
allowing
input
high
the
(DFS),
resolution
elimination
and
analog-to-digital
a
of
digital
2
S digital
external
Rev. 1.0
2
bit
S
including 32, 44.1, and 48 kHz. The digital audio
interface enables low-power operation by eliminating
the need for redundant DACs and ADCs on the audio
baseband processor.
4.5.1. Audio Data Formats
The digital audio interface operates in slave mode and
supports three different audio data formats:



In I
second rising edge of DCLK following each DFS
transition. The remaining bits of the word are sent in
order, down to the LSB. The left channel is transferred
first when the DFS is low, and the right channel is
transferred when the DFS is high.
In left-justified mode, by default the MSB is captured on
the first rising edge of DCLK following each DFS
transition. The remaining bits of the word are sent in
order, down to the LSB. The left channel is transferred
first when the DFS is high, and the right channel is
transferred when the DFS is low.
In DSP mode, the DFS becomes a pulse with a width of
1DCLK period. The left channel is transferred first,
followed right away by the right channel. There are two
options in transferring the digital audio data in DSP
mode: the MSB of the left channel can be transferred on
the first rising edge of DCLK following the DFS pulse or
on the second rising edge.
In all audio formats, depending on the word size, DCLK
frequency, and sample rates, there may be unused
DCLK cycles after the LSB of each word before the next
DFS transition and MSB of the next word. In addition, if
preferred, the user can configure the MSB to be
captured on the falling edge of DCLK via properties.
The number of audio bits can be configured for 8, 16,
20, or 24 bits.
4.5.2. Audio Sample Rates
The device supports a number of industry-standard
sampling rates including 32, 44.1, and 48 kHz. The
digital audio interface enables low-power operation by
eliminating the need for redundant DACs on the audio
baseband processor.
I
Left-Justified
DSP Mode
2
2
S mode, by default the MSB is captured on the
S
Si4704/05-D60
21