CAT24M01WI-GT3 ON Semiconductor, CAT24M01WI-GT3 Datasheet - Page 6

• Manufacturer Part Number: CAT24M01WI-GT3
• Description: IC, EEPROM, 1MBIT SERIAL 1MHZ SOIC-8
• Manufacturer: ON Semiconductor

Specifications of CAT24M01WI-GT3

• Memory Size: 1Mbit
• Memory Configuration: 128K X 8
• Ic Interface Type: I2C
• Clock Frequency: 1MHz
• Supply Voltage Range: 1.8V To 5.5V
• Memory Case Style: SOIC
• No. Of Pins: 8
• Rohs Compliant: Yes

WRITE OPERATIONS
Byte Write
by Slave address, two byte address and data to be written
(Figure 6). The Slave acknowledges all 4 bytes, and the
Master then follows up with a STOP, which in turn starts the
internal Write operation (Figure 7). During internal Write,
the Slave will not acknowledge any Read or Write request
from the Master.
Page Write
in 512 pages of 256 bytes each. The most significant 9 bits
of the address word (a16 from the Slave Address byte and
most significant Address byte) identify the page and the last
8 bits identify the byte within the page. The 17−bit address
word (a16 from the Slave Address byte followed by two
address bytes) points to the first byte to be written. Up to 256
bytes can be written in one Write cycle (Figure 8).
incremented after each data byte is loaded. If the Master
transmits more than 256 data bytes, then earlier bytes will be
overwritten by later bytes in a ‘wrap−around’ fashion
(within the selected page). The internal Write cycle starts
immediately following the STOP.
by Byte Write or Page Write instructions will replace data
previously stored at the corresponding address locations,
while data stored at all other address locations within the
same page will be refreshed. Thus, whether writing one
byte or 256 bytes to a page, the entire page will be
reprogrammed with the corresponding combination of
new and old data.
In Byte Write mode the Master sends a START, followed
The CAT24M01 contains 131,072 bytes of data, arranged
The internal byte address counter is automatically
During an internal Write operation, new data provided
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Acknowledge Polling
CAT24M01 is busy writing or is ready to accept commands.
Polling is implemented by interrogating the device with a
‘Selective Read’ command (see READ OPERATIONS).
as long as internal Write is in progress.
Hardware Write Protection
protected against Write operations. If the WP pin is left
floating or is grounded, it has no impact on the operation of
the CAT24M01. The state of the WP pin is strobed on the last
falling edge of SCL immediately preceding the first data
byte (Figure 9). If the WP pin is HIGH during the strobe
interval, the CAT24M01 will not acknowledge the data byte
and the Write request will be rejected.
Delivery State
Acknowledge polling can be used to determine if the
The CAT24M01 will not acknowledge the Slave address,
With the WP pin held HIGH, the entire memory is
The CAT24M01 is shipped erased, i.e., all bytes are FFh.