CAT24M01WI-GT3 ON Semiconductor, CAT24M01WI-GT3 Datasheet - Page 8

• Manufacturer Part Number: CAT24M01WI-GT3
• Description: IC, EEPROM, 1MBIT SERIAL 1MHZ SOIC-8
• Manufacturer: ON Semiconductor

Specifications of CAT24M01WI-GT3

• Memory Size: 1Mbit
• Memory Configuration: 128K X 8
• Ic Interface Type: I2C
• Clock Frequency: 1MHz
• Supply Voltage Range: 1.8V To 5.5V
• Memory Case Style: SOIC
• No. Of Pins: 8
• Rohs Compliant: Yes

READ OPERATIONS
Immediate Address Read
points to the data byte immediately following the last byte
accessed by a previous operation. If that ‘previous’ byte was
the last byte in memory, then the address counter will point
to the 1st memory byte, etc.
with a Slave address containing a ‘1’ in the R/W bit position
(Figure 10), it will acknowledge (ACK) in the 9th clock cycle,
and will then transmit data being pointed at by the internal
address counter. The Master can stop further transmission by
issuing a NoACK, followed by a STOP condition.
Selective Read
different from the one stored in the internal address counter.
In standby mode, the CAT24M01 internal address counter
When, following a START, the CAT24M01 is presented
The Read operation can also be started at an address
BUS ACTIVITY:
BUS ACTIVITY:
SDA LINE
SDA LINE
MASTER
MASTER
SCL
SDA
S
S
T
A
R
T
ADDRESS
SLAVE
ADDRESS
SLAVE
BUS ACTIVITY:
A
C
K
SDA LINE
MASTER
Figure 10. Immediate Address Read Timing
DATA n
A
C
K
DATA OUT
8th Bit
Figure 12. Sequential Read Timing
Figure 11. Selective Read Timing
8
a
15
S
S
T
A
R
T
− a
BYTE ADDRESS
C
A
K
8
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ADDRESS
SLAVE
DATA n+1
A
C
K
8
a
7
9
A
C
K
The address counter can be initialized by performing a
‘dummy’ Write operation (Figure 11). Here the START is
followed by the Slave address (with the R/W bit set to ‘0’)
and the desired two byte address. Instead of following up
with data, the Master then issues a 2nd START, followed by
the ‘Immediate Address Read’ sequence, as described
earlier.
Sequential Read
by the CAT24M01, then the device will continue
transmitting as long as each data byte is acknowledged by
the Master (Figure 12). If the end of memory is reached
during sequential Read, then the address counter will
‘wrap−around’ to the beginning of memory, etc. Sequential
Read works with either ‘Immediate Address Read’ or
‘Selective Read’, the only difference being the starting byte
address.
− a
NO ACK
A
C
K
If the Master acknowledges the 1st data byte transmitted
0
DATA
DATA n+2
A
C
K
S
S
T
A
R
T
ADDRESS
O
N
A
C
K
SLAVE
O
P
S
T
P
A
C
K
STOP
A
C
K
DATA n+x
DATA
O
N
A
C
K
O
S
P
P
T
O
N
A
C
K
O
S
T
P
P