S29GL128S10DHI020 Spansion Inc., S29GL128S10DHI020 Datasheet - Page 38

• Manufacturer Part Number: S29GL128S10DHI020
• Manufacturer: Spansion Inc.

Specifications of S29GL128S10DHI020

• Lead Free Status / Rohs Status: Compliant

5.4
38
5.4.1
Status Monitoring
Status Register
Software Reset does not affect EA mode. Reset commands are ignored once programming or erasure has
begun, until the operation is complete. Software Reset does not affect outputs; it serves primarily to return to
Read mode from an ASO mode or from a failed program or erase operation.
Software Reset may cause a return to Read mode from undefined states that might result from invalid
command sequences. However, a Hardware Reset may be required to return to normal operation from some
undefined states.
There is no software reset latency requirement. The reset command is executed during the t
There are three methods for monitoring EA status. Previous generations of the S29GL flash family used the
methods called Data Polling and Ready/Busy# (RY/BY#) Signal. These methods are still supported by the
S29GL-S family. One additional method is reading the Status Register. Only the Status Register method will
be supported in future technology nodes.
The status of program and erase operations is provided by a single 16-bit status register. The Status Register
Read command is written followed by one read access of the status register information. The contents of the
status register is aliased (overlaid) in all locations of the device address space. The overlay is in effect for one
read access, specifically the next read access that follows the Status Register Read command. After the one
status register access, the Status Register ASO is exited. The CE# or OE# signal must go High following the
status register read access for t
Register Read command was issued.
The status register contains bits related to the results - success or failure - of the most recently completed
Embedded Algorithms (EA):
 Erase Status (bit 5),
 Program Status (bit 4),
 Write Buffer Abort (bit 3),
 Sector Locked Status (bit 1),
 RFU (bit 0).
and, bits related to the current state of any in process EA:
 Device Busy (bit 7),
 Erase Suspended (bit 6),
 Program Suspended (bit 2),
The current state bits indicate whether an EA is in process, suspended, or completed.
The upper 8 bits (bits 15:8) are reserved. These have undefined High or Low value that can change from one
status read to another. These bits should be treated as don't care and ignored by any software reading status.
The Clear Status Register Command will clear to 0 the results related bits of the status register but will not
affect the current state bits.
D a t a
CEPH
S h e e t
GL-S MirrorBit
/t
OEPH
time to return to the address space active at the time the Status
( A d v a n c e
®
Family
I n f o r m a t i o n )
S29GL_128S_01GS_00_01 February 11, 2011
WPH
period.