EVALAD7762EB Analog Devices Inc, EVALAD7762EB Datasheet - Page 3

• Manufacturer Part Number: EVALAD7762EB
• Manufacturer: Analog Devices Inc

Specifications of EVALAD7762EB

• Lead Free Status / Rohs Status: Not Compliant

Preliminary Technical Data
HARDWARE DESCRIPTION
POWER SUPPLIES
The EVAL-AD776xEDZ must be powered using a power supply
that applies a 7.5 V between the V+ and GND terminals of
Connector J2.
This 7.5 V supply is then regulated on board using ADP3334
devices (U9 and U6) to provide the 2.5 V and 5 V signals required
by the AD7760/AD7762/AD7763 device. Supplies AV
and AV
device. The AD7760/AD7762/AD7763 pins AV
DV
A separately regulated 2.5 V supply is used to power all digital
functionality on the EVAL-AD7760/AD7762/AD7763EDZ ex-
cluding the AD7760/AD7762/AD7763 device. An individually
regulated 5 V supply also supplies the crystal oscillator and clock
buffer devices on the EVAL-AD7760/AD7762/AD7763EDZ.
Setting LK1 to A means that the MCLK buffer is powered by 5 V,
enabling the AD7760/AD7762/AD7763 device to be operated
using an MCLK signal with an amplitude of 5 V.
DIFFERENTIAL INPUT
The differential input to the AD7760/AD7762/AD7763 device is
applied through the connector marked J1. This is an XLR audio
standard connector. The differential inputs are routed through
the AD7760/AD7762/AD7763 on-board differential amplifier
using the external circuit components as detailed in the AD7760/
AD7762/AD7763 data sheets.
STANDALONE OPERATION
The EVAL-AD776xEDZ can be used in a standalone manner
(that is, without using the EVAL-CED1Z). In this case, however,
the user must provide all the required interface communications
and be able to provide a means to acquire the output data from the
board. In the case where this is desirable, the FPGA can be
disabled to allow the data from the AD7760/AD7762/
AD7763 device to be taken from Header J9 (marked “DATA”).
DD
are supplied by a voltage of 2.5 V.
DD4
are the 5 V supplies to the AD7760/AD7762/AD7763
DD1
, V
DRIVE
DD2
, AV
, and
Rev. PrA | Page 3 of 24
DD3
,
The FPGA outputs can be set to three-state by putting LK4 in
Position A. This means that the output data is routed through
Buffers U12 and U13 and is available at Header J9. The enable
mechanism for U12 and U13 is set by LK3. See the Link Options
section for details.
The output voltage of Buffers U12 and U13 can be set by
inputting the desired voltage to Connector J14 (marked “External
IO Voltage 2.5 V to 5 V”). The control signals needed for the
AD7760/AD7762/AD7763 interface can be attached to Header
J10 (marked “Control”). Otherwise, the signals RD /WR, CS ,
and MCLK can be connected to J5, J4, and J8 (SMB connectors),
respectively. Note that in the case of the AD7763, the interface
signals required for the part are output on J9 (marked “DATA”)
and the SMB connectors CS and RD /WR become redundant.
DECOUPLING AND LAYOUT RECOMMENDATIONS
The data sheets of the AD7760, AD7762, and AD7763 devices
contain specific information about the decoupling and layout
recommendations required to achieve the optimum specifications.
The EVAL-AD7760/AD7762/AD7763EDZ adhere to these recom-
mendations completely and are designed as the blueprint for
users of the AD7760, AD7762, and AD7763 devices.
The EVAL-AD7760/AD7762/AD7763EDZ are 4-layer boards.
One layer is a dedicated ground plane. All supplies to devices on
the EVAL-AD7760/AD7762/AD7763EDZ are decoupled to this
ground plane. In addition to the PCB’s top and bottom layers,
there is also a layer for routing power signals. All layers of the
board are detailed in the Evaluation Board Schematic and
Artwork section.
In addition, the exposed paddle of an AD7760, AD7762, or
AD7763 device is connected by multiple vias to this ground
plane. The exposed paddle is not connected to any of the
ground pins on the AD7760, AD7762, or AD7763 device.
EVAL-AD7760/AD7762/AD7763EDZ