ADC101S021EVAL National Semiconductor, ADC101S021EVAL Datasheet
ADC101S021EVAL
Specifications of ADC101S021EVAL
ADC101S021EVAL Summary of contents
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... ADC101S021 8-bit ADC081S021 Connection Diagram Ordering Information Order Code ADC101S021CISD ADC101S021CISDX ADC101S021CIMF ADC101S021CIMFX ADC101S021EVAL TRI-STATE ® registered trademark of National Semiconductor Corporation. © 2008 National Semiconductor Corporation Features ■ Specified over a range of sample rates. ■ 6-lead LLP and SOT-23 packages ■ ...
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Block Diagram Pin Descriptions and Equivalent Circuits Pin No. Symbol ANALOG I/O V Analog input. This signal can range from DIGITAL I/O 4 SCLK Digital clock input. This clock directly controls the conversion and readout ...
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... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Analog Supply Voltage V A Voltage on Any Analog Pin to GND Voltage on Any Digital Pin to GND Input Current at Any Pin (Note 3) Package Input Current (Note 3) Power Consumption 25° ...
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Symbol Parameter ANALOG INPUT CHARACTERISTICS V Input Range Leakage Current DCL C Input Capacitance INA DIGITAL INPUT CHARACTERISTICS V Input High Voltage IH V Input Low Voltage IL I Input Current IN C Digital Input Capacitance IND ...
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Symbol Parameter t Aperture Delay AD t Aperture Jitter AJ ADC101S021 Timing Specifications The following specifications apply for ksps to 200 ksps, Boldface limits apply for T SAMPLE Symbol Parameter t Minimum CS Pulse Width CS ...
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Timing Diagrams www.national.com FIGURE 1. Timing Test Circuit FIGURE 2. ADC101S021 Serial Timing Diagram 6 20145308 20145306 ...
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Specification Definitions ACQUISITION TIME is the time required to acquire the input voltage. That is time required for the hold capacitor to charge up to the input voltage. APERTURE DELAY is the time between the fourth falling SCLK ...
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Typical Performance Characteristics MHz to 4 MHz 100 kHz unless otherwise stated. SCLK IN DNL MHz SCLK DNL MHz SCLK DNL vs. Clock Frequency www.national.com T = +25°C, f ...
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SNR vs. Clock Frequency 20145363 SFDR vs. Clock Frequency 20145367 Spectral Response 5.25V MHz SCLK 20145369 SINAD vs. Clock Frequency THD vs. Clock Frequency Power Consumption vs. Throughput MHz SCLK 9 ...
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Applications Information 1.0 ADC101S021 OPERATION The ADC101S021 is a successive-approximation analog-to- digital converter designed around a charge-redistribution dig- ital-to-analog converter core. Simplified schematics of the ADC101S021 in both track and hold modes are shown in Figure 3 and Figure 4, ...
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ADC101S021 TRANSFER FUNCTION The output format of the ADC101S021 is straight binary. Code transitions occur midway between successive integer LSB values. The LSB width for the ADC101S021 is V The ideal transfer characteristic is shown in Figure 5. The ...
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CS is again brought low. After sixteen SCLK cycles, SDATA returns to TRI-STATE. Another conversion may be started, after t by bringing CS low again. 7.2 Shutdown Mode Shutdown mode ...
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Load dis- charge currents will cause "ground bounce" noise in the sub- strate that will degrade noise performance if that current is large enough. The larger the output capacitance, the more current ...
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Physical Dimensions Order Number ADC101S021CISD or ADC101S021CISDX www.national.com inches (millimeters) unless otherwise noted 6-Lead LLP NS Package Number SDB06A 6-Lead SOT-23 Order Number ADC101S021CIMF, ADC101S021CIMFX NS Package Number MF06A 14 ...
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Notes 15 www.national.com ...
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