ADC101S021EVAL National Semiconductor, ADC101S021EVAL Datasheet - Page 12

• Manufacturer Part Number: ADC101S021EVAL
• Manufacturer: National Semiconductor

Specifications of ADC101S021EVAL

• Lead Free Status / Rohs Status: Not Compliant

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before the start of the next conversion, which begins when
CS is again brought low.
After sixteen SCLK cycles, SDATA returns to TRI-STATE.
Another conversion may be started, after t
by bringing CS low again.
7.2 Shutdown Mode
Shutdown mode is appropriate for applications that either do
not sample continuously, or it is acceptable to trade through-
put for power consumption. When the ADC101S021 is in
shutdown mode, all of the analog circuitry is turned off.
To exit shutdown mode, bring CS back low. Upon bringing
CS low, the ADC101S021 will begin powering up (power-up
time is specified in the Timing Specifications table). This pow-
er-up delay results in the first conversion result being unus-
able. The second conversion performed after power-up,
however, is valid, as shown in Figure 9.
If CS is brought back high before the 10th falling edge of
SCLK, the device will return to shutdown mode. This is done
to avoid accidentally entering normal mode as a result of
noise on the CS line. To exit shutdown mode and remain in
normal mode, CS must be kept low until after the 10th falling
edge of SCLK. The ADC101S021 will be fully powered-up af-
ter 16 SCLK cycles.
8.0 POWER MANAGEMENT
The ADC101S021 takes time to power-up, either after first
applying V
mode. This corresponds to one "dummy" conversion for any
SCLK frequency within the specifications in this document.
After this first dummy conversion, the ADC101S021 will per-
form conversions properly. Note that the t
be included between the first dummy conversion and the sec-
ond valid conversion.
When the V
power up in either of the two modes: normal or shutdown. As
such, one dummy conversion should be performed after start-
up, as described in the previous paragraph. The part may then
A
, or after returning to normal mode from shutdown
A
supply is first applied, the ADC101S021 may
QUIET
QUIET
FIGURE 8. Entering Shutdown Mode
FIGURE 9. Entering Normal Mode
time must still
has elapsed,
12
To enter shutdown mode, a conversion must be interrupted
by bringing CS high anytime between the second and tenth
falling edges of SCLK, as shown in Figure 8. Once CS has
been brought high in this manner, the device will enter shut-
down mode, the current conversion will be aborted and SDA-
TA will enter TRI-STATE. If CS is brought high before the
second falling edge of SCLK, the device will not change
mode; this is to avoid accidentally changing mode as a result
of noise on the CS line.
be placed into either normal mode or the shutdown mode, as
described in Sections 7.1 and 7.2.
When the ADC101S021 is operated continuously in normal
mode, the maximum throughput is f
be traded for power consumption by running f
imum specified rate and performing fewer conversions per
unit time, raising the ADC101S021 CS line after the 10th and
before the 15th fall of SCLK between conversions. A plot of
typical power consumption versus throughput is shown in the
Typical Performance Curves section. To calculate the power
consumption for a given throughput, multiply the fraction of
time spent in the normal mode by the normal mode power
consumption and add the fraction of time spent in shutdown
mode multiplied by the shutdown mode power consumption.
Note that the curve of power consumption vs. throughput is
essentially linear. This is because the power consumption in
the shutdown mode is so small that it can be ignored for all
practical purposes.
9.0 POWER SUPPLY NOISE CONSIDERATIONS
The charging of any output load capacitance requires current
from the power supply, V
the supply to charge the output capacitance will cause voltage
variations on the supply. If these variations are large enough,
they could degrade SNR and SINAD performance of the ADC.
Furthermore, discharging the output capacitance when the
digital output goes from a logic high to a logic low will dump
A
. The current pulses required from
SCLK
/ 20. Throughput may
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SCLK
at its max-
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