AC101LKQT Broadcom, AC101LKQT Datasheet - Page 15

• Manufacturer Part Number: AC101LKQT
• Manufacturer: Broadcom

Specifications of AC101LKQT

• Number Of Receivers: 1
• Data Rate: 10/100Mbps
• Package Type: TQFP
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Lead Free Status / Rohs Status: Not Compliant

03/10/03
Many of the pin have multiple functions. The multifunction pins are designated by bold style of the pin number. The separate
descriptions of these pins are listed in the proper sections. Designers must assure that they have identified all modes of
operation prior to final design.
Signal types:
•
•
•
•
•
•
•
•
All digital pins are bidirectional pins.
Document
PIN #
1
2
2
3
4
5
6
7
8
9
10
11
12
13
14
15
B = Bidirection pin
P = Power pin
G = Ground pin
AI = Analog Input pin
AO = Analog output pin
D = Internal pull-down pin
U = Internal pull-up pin
= Active low
AC101L-DS05-R
PIN name
VCC
GND
GND
RXDV
RX_CLK
RXER
GND
VCC
TXER
TX_CLK
TXEN
TXD0
TXD1
TXD2
TXD3
COL
Section 2: Pin Des cr iptions
Type
P
G
G
B
B
B
G
P
B
B
B
B
B
B
B
B
D
D
D
D
D
D
D
D
D
D
D
Table 1: Pinout and Signal Definitions
Description
+2.5 V power supply.
Ground
Ground
RXDV (active HIGH output): Receive Data Valid is the output signal in the MII mode.
RXDV is active HIGH to indicate that the receive frame is in progress, and that the data
stream present on the RXD output pins is valid.
Input function is reserved. This pin must be pulled low externally.
RX_CLK (Output): Receive clock in MII mode. RX_CLK is 25-MHz output in 100BASE
and 2.5-MHz output in 10BASE. This clock is recovered from the incoming data on the
cable inputs.
Input function is reserved. This pin must be pulled low externally.
RXER (active HIGH output): asserted to indicate that an invalid symbol or bad SSD is
detected in MII modes.
Ground
+2.5 V power supply.
TXER (active HIGH input): Transmits an error in the MII interface. When TXER is
asserted for one or more TX_CLK periods while TXEN is also asserted, the PHY emits
one or more symbols that are not part of the valid data or delimiter set somewhere in
the frame being transmitted. The relative position of the error within the frame need not
be preserved.
TX_CLK (output): Transmits the clock signal of the MII mode. TX_CLK is
25-MHz output in 100BASE operation and 2.5 MHz in 10BASE operation. This clock is
a continuously-driven output, generated from the XI (crystal input) pin.
TXEN (active HIGH input): Transmits the Enable signal in the MII interfaces. TXEN is
asserted by the MAC to indicate that valid data is present on TXD[3:0].
TXD0: Transmits data input for the MII interface.
TXD1: Transmits data input for the MII interface.
TXD2: Transmits data input for the MII interface.
TXD3: Transmits data input for MII interface.
COL (active HIGH output): This pin must be pulled low externally. It is the collision
detect signal in the MII interface. In half-duplex mode, COL active high output indicates
that a collision has occurred. In full-duplex mode, COL remains low.
B roa dcom
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