ADG738BRUZ Analog Devices Inc, ADG738BRUZ Datasheet - Page 9

• Manufacturer Part Number: ADG738BRUZ
• Description: IC MUX/DEMUX 8X1 16TSSOP
• Manufacturer: Analog Devices Inc
• Type: Analog Multiplexerr

Specifications of ADG738BRUZ

• Function: Multiplexer/Demultiplexer
• Circuit: 1 x 8:1
• On-state Resistance: 4.5 Ohm
• Voltage Supply Source: Single Supply
• Voltage - Supply, Single/dual (±): 2.7 V ~ 5.5 V
• Current - Supply: 10µA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP (0.173", 4.40mm Width)
• No. Of Channels: 8
• Bandwidth: 65MHz
• On State Resistance Max: 4.5ohm
• Turn Off Time: 10ns
• Turn On Time: 20ns
• Supply Voltage Range: 2.7V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Package: 16TSSOP
• Maximum On Resistance: 11@3V Ohm
• Maximum High Level Output Current: 120 mA
• Multiplexer Architecture: 8:1
• Maximum Turn-off Time: 14(Typ)@3V ns
• Maximum Turn-on Time: 40(Typ)@3V ns
• Power Supply Type: Single
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

GENERAL DESCRIPTION
The ADG738 and ADG739 are serially controlled, 8-channel
and dual 4-channel Matrix Switches respectively. While provid-
ing the normal multiplexing and demultiplexing functions, these
parts also provide the user with more flexibility as to where their
signal may be routed. Each bit of the 8-bit serial word corresponds
to one switch of the part. A Logic 1 in the particular bit position
turns on the switch, while a Logic 0 turns the switch off. Because
each switch is independently controlled by an individual bit, this
provides the option of having any, all, or none of the switches ON.
This feature may be particularly useful in the demultiplexing
application where the user may wish to direct one signal from
the drain to a number of outputs (sources). Care must be taken,
however, in the multiplexing situation where a number of inputs
may be shorted together (separated only by the small on resis-
tance of the switch).
When changing the switch conditions, a new 8-bit word is writ-
ten to the input shift register. Some of the bits may be the same
as the previous write cycle, as the user may not wish to change
the state of some switches. In order to minimize glitches on the
output of these switches, the part cleverly compares the state of
switches from the previous write cycle. If the switch is already
in the ON condition, and is required to stay ON, there will
be minimal glitches on the output of the switch.
POWER-ON RESET
On power-up of the device, all switches will be in the OFF con-
dition and the internal shift register is filled with zeros and will
remain so until a valid write takes place.
SERIAL INTERFACE
The ADG738 and ADG739 have a 3-wire serial interface
(SYNC, SCLK, and DIN), which is compatible with SPI,
QSPI, MICROWIRE interface standards and most DSPs. Fig-
ure 1 shows the timing diagram of a typical write sequence.
Data is written to the 8-bit shift register via DIN under the
control of the SYNC and SCLK signals. Data may be written to
the shift register in more or less than eight bits. In each case
the shift register retains the last eight bits that were written.
When SYNC goes low, the input shift register is enabled. Data
from DIN is clocked into the shift register on each falling edge
of SCLK. Each bit of the 8-bit word corresponds to one of the
eight switches. Figure 15 shows the contents of the input shift
register. Data appears on the DOUT pin on the rising edge of
SCLK suitable for daisy-chaining, delayed, of course, by eight
bits. When all eight bits have been written into the shift register,
the SYNC line is brought high again. The switches are updated
with the new configuration and the input shift register is
disabled. With SYNC held high, any further data or noise on
the DIN line will have no effect on the shift register.
DB7 (MSB)
S8
S7
S6
DATA BITS
S5
S4
S3
DB0 (LSB)
S2
S1
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the ADG738/ADG739 is via a
serial bus that uses standard protocol compatible with micro-
controllers and DSP processors. The communications channel
is a 3-wire (minimum) interface consisting of a clock signal, a data
signal, and a synchronization signal. The ADG738/ADG739 requires
an 8-bit data word with data valid on the falling edge of SCLK.
Data from the previous write cycle is available on the DOUT
pin. The following figures illustrate simple 3-wire interfaces
with popular microcontrollers and DSPs.
ADSP-21xx to ADG738/ADG739
An interface between the ADG738/ADG739 and the ADSP-
21xx is shown in Figure 16. In the interface example shown,
SPORT0 is used to transfer data to the Matrix Switch. The
SPORT control register should be configured as follows: internal
Clock operation, alternate framing mode; active low framing signal.
Transmission is initiated by writing a word to the Tx register
after the SPORT has been enabled. As the data is clocked out of
the DSP on the rising edge of SCLK, no glue logic is required
to interface the DSP to the Matrix Switch. The update of each
switch condition takes place automatically when TFS is taken high.
8051 Interface to ADG738/ADG739
A serial interface between the ADG738/ADG739 and the 8051
is shown in Figure 17. TXD of the 8051 drives SCLK of the
ADG738/ADG739, while RXD drives the serial data line, DIN.
P3.3 is a bit-programmable pin on the serial port and is used to
drive SYNC.
The 8051 provides the LSB of its SBUF register as the first bit
in the data stream. The user will have to ensure that the data in
the SBUF register is arranged correctly as the switch expects
MSB first.
When data is to be transmitted to the Matrix Switch, P3.3 is
taken low. Data on RXD is clocked out of the microcontroller
on the rising edge of TXD and is valid on the falling edge. As a
result no glue logic is required between the ADG738/ADG739
and microcontroller interface.
80C51/80L51*
ADSP-21xx*
*ADDITIONAL PINS OMITTED FOR CLARITY.
*ADDITIONAL PINS OMITTED FOR CLARITY.
SCLK
P3.3
RXD
TFS
TXD
DT
ADG738/ADG739
SYNC
DIN
SCLK
SYNC
DIN
SCLK
ADG738/
ADG739
ADG738/
ADG739