CORE1553BRT-SR MICROSEMI, CORE1553BRT-SR Datasheet

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... Compiler Compliant VHDL Simulators and OVI-Compliant Verilog Simulators Verification and Compliance • Actel-Developed Simulation Testbench Implements a Subset of the RT Test Plan (MIL-HDBK-1553A) • Test Systems, Inc. (TSI) certified Core1553BRT to MIL-STD-1553B (RT Validation Test Plan MIL-HDBK- 1553, Appendix A) Contents General Description ................................................... 2 Core1553BRT Device Requirements .......................... 4 Core1553BRT Verification and Compliance ...

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... Core1553BRT MIL-STD-1553B Remote Terminal General Description Core1553BRT provides a complete, dual-redundant MIL-STD-1553B remote terminal (RT) apart from the transceivers required to interface to the bus. A typical system implementation using the Core1553BRT is shown in Figure 2 on page 3. ADC Address Mapper Memory Command Legality Checker Figure 1 • Typical Core1553BRT System At a high level, Core1553BRT simply provides a set of memory mapped sub-addresses that ‘ ...

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... The decoder detects whether a command or data word is received, and also performs Manchester encoding and parity error checking. The backend interface for the Core1553BRT allows a simple connection to a memory device or direct connection to other devices, such as analog-to-digital converters, etc. The access rates to this memory are slow with one read or write every 20µ ...

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... RT validation test plan MIL-HDBK-1553A, Appendix A. Core1553BRT Fail Safe State Machines The logic design of Core1553BRT implements fails safe state machines. All state machines include illegal state detection logic state machine should ever enter an Table 1 • Device Utilization Family Comb ...

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... Command BC Mode Message Next Data Gap Command BC RT Status Message Next Word Gap Command BC Next Command v6.0 Core1553BRT MIL-STD-1553B Remote Terminal shows the message formats. BC Next Command BC Next Command RT2 Response Status Message Time Word Gap Command BC Message Next Gap Command ...

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... Core1553BRT MIL-STD-1553B Remote Terminal Word Formats There are only three types of words in a 1553B message: a command word (CW), a data word (DW), and a status word (SW). Each word consists of a three-bit sync pattern, 16 bits of data and a parity bit, providing the 20-bit word (Figure 4). ...

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... This goes high if the core fails to read or write data to the backend interface within the required time. This can be caused by the backend not asserting MEMGNTn fast enough or asserting MEMWAITn for too long. Used to clear the MEMFAIL and other internal error conditions. Must be held high for greater than two clock cycles. v6.0 Core1553BRT MIL-STD-1553B Remote Terminal 7 ...

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... Core1553BRT MIL-STD-1553B Remote Terminal Command Legalization Interface The core checks the validity of all 1553B command words. In RTL and netlist versions of the core, the logic may be implemented externally to the core. The command word is provided, and the logic must generate the command valid input. The command legalization ...

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... Data Bus Enable (active high). This signal is high when the core is requesting the memory bus has been granted control and is waiting to write data intended to enable any bidirectional drivers that may be implemented on the memory data bus. v6.0 Core1553BRT MIL-STD-1553B Remote Terminal µ the WRTTSW 9 ...

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... In FSM_ERROR Out 1 0 Standard Memory Address Map Core1553BRT requires an external 2,048x16 memory device. This memory is split into (64) 32-word data buffers. Each of the 30 sub-addresses has a receive and a transmit buffer, as shown in The memory allocated to the unused receive sub- addresses 0 and 31 is used to provide status information back to the rest of the system ...

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... The core only writes to these addresses. (except when SA30LOOP is high) The core only reads from these addresses. RX Memory Read TX Memory Write Figure 5 • Using Internal FPGA Memory Blocks v6.0 Core1553BRT MIL-STD-1553B Remote Terminal Write BUSAINEN BUSAINP BUSAINN Backend Interface BUSAINH BUSAOUTP BUSAOUTN Read ...

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... Core1553BRT MIL-STD-1553B Remote Terminal Memory Address Mapping The core supports an external memory address mapper that allows the RT memory allocation to be easily customized. To use this function the CMDVAL output must be latched by the ADDRLAT signal as shown in Figure 6. Then, the address mapper function can map the ...

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... Status Word Settings The Core1553BRT sets bits in the 1553B status word in compliance with MIL-STD-1553B. This is summarized in Table 8 • Status Word Bit Settings Bit Function 15:11 RT Address Equals the RTADDR input 10 Message Error Is set whenever the RT detects a message error 9 Instrumentation Always ‘0’ ...

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... Core1553BRT MIL-STD-1553B Remote Terminal Table 9 • Transfer Status Word Bit Name 15 USED This bit is set to ‘1’ at the end of the transmit or receive command. 14 OKAY Indicates that no errors are detected, i.e. bits are all ‘0’ 13 BUSN Indicates on which bus the command was received ...

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... Loopback Tests The Core1553BRT performs loopback testing on all of its transmissions. The transmit data is fed back into the receiver and each transmitted word is compared error is detected, the loopback fail bit is set in the TSW and also in the BIT word. Table 10 • Supported Mode Codes ...

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... Core1553BRT MIL-STD-1553B Remote Terminal Error Detection Table 11 • Error Detection Error Condition Command Word 1. Parity or Manchester Encoding Errors 2. Incorrect SYNC waveform Mode Codes 1. Illegal Mode Code or invalid sub-address (from internal or external legality block) Broadcast Data Commands 1. TX bit set in Command word Data Word 1 ...

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... Built-in Test Support The Core1553BRT provides a BIT word. This is used to communicate fail information back to the bus controller. The BIT word contains information from Command Legalization Interface 1553B commands can be legalized in two ways with the Core1553BRT. For RTL versions, one of the modules in the source code can be edited to legalize or make illegal Table 12 • ...

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... Command Legality Checker Figure 9 • Typical CPU and Memory-Based RT System 1 8 Typical RT Systems The Core1553BRT can be used in systems with and without backend memory. to MIL-STD-1553 implementation for a system with backend memory and a CPU to process the messages. shows a system with direct connection between the Core1553BRT and external analog-to-digital converters, etc ...

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... ADC Glue Logic DAC Command Legality Interface Figure 10 • Typical Non-Memory-Based RT System Core1553BRT MIL-STD-1553B Remote Terminal BUSAINEN RCVSTBA BUSAINP RXDAINP BUSAINN RXDAINN Backend Interface BUSAOUTINH TXINHA BUSAOUTP TXDAINP BUSAOUTN TXDAINN BUSBINEN RCVSTBA BUSBINP RXDBINP Command BUSBINN RXDBINN Legality Interface BUSBOUTINH TXINHA ...

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... Core1553BRT MIL-STD-1553B Remote Terminal Specifications Memory Write Timing – Asynchronous Mode CLK ADDRLAT MEMREQn MEMGNTn MEMCEN MEMDEN MEMCSn MEMADDR MEMOPER MEMDATA MEMWRn MEMWAITn Figure 11 • Memory Write Timing – Asynchronous Mode Memory Write Timing Table 14 • Memory Write Timing Sync Mode ...

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... Address setup time to MEMRDn low suADDR T Address hold time from MEMRDn high hdADDR T Wait setup to rising clock edge suWAIT T Data setup time to MEMRDn high suDATA Core1553BRT MIL-STD-1553B Remote Terminal Valid Address Valid Operation Data Description v6.0 Time 1 clock cycle 12.0µs 1 clock cycle 1 clock cycle 15 ...

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... Core1553BRT MIL-STD-1553B Remote Terminal Memory Write Timing – Synchronous Mode CLK ADDRLAT MEMREQn MEMGNTn MEMCEN MEMDEN MEMCSn MEMADDR MEMOPER MEMDATA MEMWRn Figure 13 • Memory Write Timing 2 2 Address Operation Data Data written here v6.0 ...

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... CMDOK CMDSTB Figure 15 • Command Word Legality Interface Timing Table 16 • Command Word Legality Interface Timing Name Description TpdCMDOK Maximum external command word legality decode delay Core1553BRT MIL-STD-1553B Remote Terminal Address Operation Data Data sampled here Current Command v6.0 Time 3µs ...

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... Core1553BRT MIL-STD-1553B Remote Terminal Address Mapper Timing CLK CMDVAL ADDRLAT MEMREQn MEMCSn Note: This figure shows the worst-case timing when a second 1553B command arrives as the core starts a backend transfer and MEMGNTn is held low. Figure 16 • Address Mapper Timing Interrupt Vector Extender Timing ...

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... Clock Requirements To meet the 1553B transmission bit rate requirements, the Core1553BRT clocks input must be 12 MHz, 16 MHz, 20 MHz or 24 MHz ±0.01%. Ordering Information Core1553BRT can be ordered through your local Actel sales representative. It should be ordered using the ...

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... Table 4 • Command Legalization Interface Table 11 • Error Detection Table 12 • BIT Word "Bus Transceivers"was updated. "Clock Requirements"was updated. v2.0 Figure 2 • Core1553BRT RT Block Diagram System were changed was updated to include Fusion. section was updated. section was updated. section was updated. ...

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... Previous version Changes in current version ( Advanced v0.2 "Product Summary" The "General Description" Figure 1 • Typical Core1553BRT System Table 1 was updated. Table 2 • 1553B Bus Interface "Command Legalization Interface" Table 4 • Command Legalization Interface Table 5 • Backend Signals Table 6 • Miscellaneous I/O " ...

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