LCMXO256E-3T100I Lattice, LCMXO256E-3T100I Datasheet - Page 20

• Manufacturer Part Number: LCMXO256E-3T100I
• Description: IC PLD 256LUTS 78I/O 100-TQFP
• Manufacturer: Lattice
• Series: MachXOr

Specifications of LCMXO256E-3T100I

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 4.9ns
• Voltage Supply - Internal: 1.14 V ~ 1.26 V
• Number Of Logic Elements/blocks: -
• Number Of Macrocells: 128
• Number Of Gates: -
• Number Of I /o: 78
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / Rohs Status: Contains lead / RoHS non-compliant

Lattice Semiconductor
Table 2-8. I/O Support Device by Device
Table 2-9. Supported Input Standards
Number of I/O Banks
Type of Input Buffers
Types of Output Buffers
Differential Output
Emulation Capability
PCI Support
Single Ended Interfaces
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
PCI
Differential Interfaces
BLVDS
1. Top Banks of MachXO1200 and MachXO2280 devices only.
2. MachXO1200 and MachXO2280 devices only.
2
Single-ended
(all I/O Banks)
Single-ended buffers
with complementary
outputs (all I/O Banks)
All I/O Banks
No
1
2
MachXO256
, LVDS
Input Standard
2
, LVPECL
2
, RSDS
4
Single-ended
(all I/O Banks)
Single-ended buffers
with complementary
outputs (all I/O Banks)
All I/O Banks
No
MachXO640
2
2-17
3.3V
√
√
√
√
√
√
2.5V
√
√
√
√
√
VCCIO (Typ.)
8
Single-ended
(all I/O Banks)
Differential Receivers
(all I/O Banks)
Single-ended buffers
with complementary
outputs (all I/O Banks)
Differential buffers with
true LVDS outputs (50%
on left and right side)
All I/O Banks
Top side only
1.8V
MachXO1200
√
√
√
√
√
√
MachXO Family Data Sheet
1.5V
√
√
√
√
√
√
1.2V
√
√
√
√
√
8
Single-ended
(all I/O Banks)
Differential Receivers
(all I/O Banks)
Single-ended buffers
with complementary
outputs (all I/O Banks)
Differential buffers with
true LVDS outputs (50%
on left and right side)
All I/O Banks
Top side only
MachXO2280
Architecture