LFXP2-5E-5MN132C Lattice, LFXP2-5E-5MN132C Datasheet
LFXP2-5E-5MN132C
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LFXP2-5E-5MN132C Summary of contents
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... LatticeXP2™ Family Data Sheet DS1009 Version 01.5, June 2008 ...
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... Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... The ispLEVER tool uses the synthesis tool output along with the constraints from its floor planning tools to place and route the design in the LatticeXP2 device. The ispLEVER tool extracts the timing from the routing and back-annotates it into the design for timing verification. ...
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... Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... PLLs PFU Blocks The core of the LatticeXP2 device is made up of logic blocks in two forms, PFUs and PFFs. PFUs can be pro- grammed to perform logic, arithmetic, distributed RAM and distributed ROM functions. PFF blocks can be pro- grammed to perform logic, arithmetic and ROM functions. Except where necessary, the remainder of this data sheet will use the term PFU to refer to both PFU and PFF blocks ...
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... Slice Routing PFU BLock Modes Logic, Ripple, ROM 2 LUT4s and 2 Registers Logic, ROM 2-3 Architecture LatticeXP2 Family Data Sheet LUT4 & LUT4 LUT4 CARRY Slice PFF Block Resources Modes Logic, Ripple, ROM Logic, Ripple, ROM Logic, Ripple, ROM 2 LUT4s Logic, ROM ...
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... F0, F1 LUT4 output register bypass signals Q0, Q1 Register outputs OFX0 Output of a LUT5 MUX OFX1 Output of a LUT6, LUT7, LUT8 FCO Slice 2 of each PFU is the fast carry chain output 2-4 LatticeXP2 Family Data Sheet SLICE OFX1 FF* To Routing LUT5 Mux ...
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... Dual Port RAM (PDPR) memory is created by using one slice as the read-write port and the other companion slice as the read-only port. The Lattice design tools support the creation of a variety of different size memories. Where appropriate, the soft- ware will construct these using distributed memory primitives that represent the capabilities of the PFU. Table 2-3 shows the number of slices required to implement different distributed RAM primitives ...
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... Lattice Semiconductor Routing There are many resources provided in the LatticeXP2 devices to route signals individually or as busses with related control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) seg- ments. The inter-PFU connections are made with x1 (spans two PFU), x2 (spans three PFU (spans seven PFU) connections. The x1 and x2 connections provide fast and effi ...
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... PLL LOCK to CLKI Clock Dividers LatticeXP2 devices have two clock dividers, one on the left side and one on the right side of the device. These are intended to generate a slower-speed system clock from a high-speed edge clock. The block operates in a ÷2, ÷4 or ÷ ...
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... LatticeXP2 devices derive primary clocks from four sources: PLL outputs, CLKDIV outputs, dedicated clock inputs and routing. LatticeXP2 devices have two to four sysCLOCK PLLs, located in the four corners of the device. There are eight dedicated clock inputs, two on each side of the device. Figure 2-6 shows the primary clock sources. ...
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... CLK DIV Clock Input Clock Input PLL Input GPLL Note: This diagram shows sources for the XP2-17 device. Smaller LatticeXP2 devices have two GPLLs. Clock Input Clock Input From Routing Primary Clock Sources to Eight Quadrant Clock Selection From Routing Clock Input ...
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... Lattice Semiconductor Secondary Clock/Control Sources LatticeXP2 devices derive secondary clocks (SC0 through SC7) from eight dedicated clock input pads and the rest from routing. Figure 2-7 shows the secondary clock sources. Figure 2-7. Secondary Clock Sources From Routing From Routing From Routing ...
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... Input From Routing CLKOP PLL GPLL CLKOS Input Sources for left edge clocks Note: This diagram shows sources for the XP2-17 device. Smaller LatticeXP2 devices have two GPLLs. Clock Input Clock Input From From Routing Routing Sources for top edge clocks ...
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... Lattice Semiconductor Primary Clock Routing The clock routing structure in LatticeXP2 devices consists of a network of eight primary clock lines (CLK0 through CLK7) per quadrant. The primary clocks of each quadrant are generated from muxes located in the center of the device. All the clock sources are connected to these muxes. Figure 2-9 shows the clock routing for one quadrant. ...
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... Lattice Semiconductor LatticeXP2-30 and smaller devices have six secondary clock regions. All devices in the LatticeXP2 family have eight secondary clocks (SC0 to SC7) which are distributed to every region. The secondary clock muxes are located in the center of the device. Figure 2-12 shows the mux structure of the secondary clock routing ...
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... Secondary Clock Edge Clock Routing LatticeXP2 devices have eight high-speed edge clocks that are intended for use with the PIOs in the implementa- tion of high-speed interfaces. Each device has two edge clocks per edge. Figure 2-15 shows the selection muxes for these clocks. ...
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... GPLL Output CLKOP GPLL Output CLKOS sysMEM Memory LatticeXP2 devices contains a number of sysMEM Embedded Block RAM (EBR). The EBR consists of 18 Kbit RAM with dedicated input and output registers. sysMEM Memory Block The sysMEM block can implement single port, dual port or pseudo dual port memories. Each block can be used in a variety of depths and widths as shown in Table 2-5 ...
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... Writes to EBR FPGA Logic Memory Cascading Larger and deeper blocks of RAMs can be created using EBR sysMEM Blocks. Typically, the Lattice design tools cascade memory transparently, based on specific design inputs. Single, Dual and Pseudo-Dual Port Modes In all the sysMEM RAM modes the input data and address for the ports are registered at the input of the memory array ...
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... RSTA RSTB GSRN For further information on the sysMEM EBR block, please see TN1137, LatticeXP2 Memory Usage Guide. EBR Asynchronous Reset EBR asynchronous reset or GSR (if used) can only be applied if all clock enables are low for a clock cycle before the reset is applied and released a clock cycle after the low-to-high transition of the reset signal, as shown in Figure 2-18. ...
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... General purpose DSP sysDSP Block Capabilities The sysDSP block in the LatticeXP2 family supports four functional elements in three 9, 18 and 36 data path widths. The user selects a function element for a DSP block and then selects the width and type (signed/unsigned) of its operands. The operands in the LatticeXP2 family sysDSP Blocks can be either signed or unsigned but not ...
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... This multiplier element implements a multiply with no addition or accumulator nodes. The two operands, A and B, are multiplied and the result is available at the output. The user can enable the input/output and pipeline registers. Figure 2-20 shows the MULT sysDSP element. x9 x18 2-19 Architecture LatticeXP2 Family Data Sheet x36 1 — — — ...
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... Multiplicand Multiplier n Input Data Register B Signed A Signed B Shift Register B Out Shift Register Multiplier m Input Data Register Input To Register Multiplier Input To Register Multiplier Shift Register A Out 2-20 Architecture LatticeXP2 Family Data Sheet m+n m+n (default) x Output Pipeline Register CLK (CLK0,CLK1,CLK2,CLK3) CE (CE0,CE1,CE2,CE3) RST(RST0,RST1,RST2,RST3) ...
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... The output register is used to store the accumulated value. The Accumulators in the DSP blocks in LatticeXP2 family can be initialized dynamically. A registered overflow signal is also available. The overflow conditions are provided later in this document. Figure 2-21 shows the MAC sysDSP element. ...
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... Register Register Reg Input Pipeline Pipe To Add/Sub Register Register Reg Input Pipeline Pipe To Add/Sub Register Register Reg Shift Register A Out 2-22 Architecture LatticeXP2 Family Data Sheet CLK (CLK0,CLK1,CLK2,CLK3) CE (CE0,CE1,CE2,CE3) RST (RST0,RST1,RST2,RST3) m+n (default) Add/Sub Output m+n+1 m+n+1 (default) (default) m+n (default) ...
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... To Add/Sub0, Add/Sub1 Register Register Input Pipeline To Add/Sub0, Add/Sub1 Register Register Input Pipeline To Add/Sub0 Register Register Input Pipeline To Add/Sub1 Register Register Shift Register A Out 2-23 Architecture LatticeXP2 Family Data Sheet CLK (CLK0,CLK1,CLK2,CLK3) CE (CE0,CE1,CE2,CE3) RST(RST0,RST1,RST2,RST3) Add/Sub0 m+n+1 SUM m+n+2 m+n+2 m+n+1 Add/Sub1 Output ...
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... Signed Operation 2-24 Architecture LatticeXP2 Family Data Sheet Two’s Complement Two’s Complement Signed 9 Bits Signed 18 Bits 000000101 000000000000000101 111111010 111111111111111010 3 2 Carry signal is generated for 1 one cycle when this ...
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... DSP design cycle in Lattice FPGAs. Optimized DSP Functions Lattice provides a library of optimized DSP IP functions. Some of the IP cores planned for the LatticeXP2 DSP include the Bit Correlator, FFT functions, FIR Filter, Reed-Solomon Encoder/Decoder, Turbo Encoder/Decoder and Convolutional Encoder/Decoder. Please contact Lattice to obtain the latest list of available DSP IP cores. ...
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... LVDS outputs. All I/O pairs can operate as inputs. PIOA IOLT0 Tristate Register Block IOLD0 Output Register Block DI Input Control Register Muxes Block CLK1 CEO LSR GSR CLK0 CEI PIOB 2-26 Architecture LatticeXP2 Family Data Sheet PADA “T” sysIO Buffer PADB “C” ...
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... PIOA and converts it as four data streams, IPOS0A, IPOS1A, IPOS0B and IPOS1B. Figure 2-26 shows the diagram using this gearbox function. For more information on this topic, please see TN1138, LatticeXP2 High Speed I/O Interface. LatticeXP2 Family Data Sheet Description Clock enables for input and output block fl ...
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... Q D D-Type D-Type DDRSRC SDR & Sync DDR Registers Registers D-Type D-Type D-Type Gearbox Configuration Bit 2-28 Architecture LatticeXP2 Family Data Sheet 2 INCK To DQS Delay Block INDD Clock Transfer Registers IPOS0A QPOS0A D-Type 1 /LATCH D-Type IPOS1A QPOS1A Q D-Type 1 D-Type /LATCH To Routing 2 ...
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... Lattice Semiconductor shows the diagram using this gearbox function. For more information on this topic, see TN1138, LatticeXP2 High Speed I/O Interface. Figure 2-27. Output and Tristate Block TD Tristate Logic ONEG1 OPOS1 Q ONEG0 D * D-Type OPOS0 D-Type CLKA Clock Transfer Registers ECLK1 ECLK2 ...
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... Signal Descriptions table. The DQS signal from the bus is used to strobe the DDR data from the memory into input register blocks. For additional information on using DDR memory support please see TN1138, LatticeXP2 High Speed I/O Interface. LatticeXP2 Family Data Sheet ...
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... Lattice Semiconductor Figure 2-28. DQS Input Routing (Left and Right) DQS Figure 2-29. DQS Input Routing (Top and Bottom) DQS LatticeXP2 Family Data Sheet PADA "T" PIO A LVDS Pair PADB "C" PIO B PADA "T" PIO A LVDS Pair PADB "C" PIO B PADA "T" ...
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... Left & Right Sides DQS Input Spans 18 PIOs Top & Bottom Sides I/O Bank 0 I/O Bank 1 DDR_DLL DDR_DLL (Right) (Left) I/O Bank 5 I/O Bank 4 2-32 Architecture LatticeXP2 Family Data Sheet ECLK1 ECLK2 Delayed DQS Polarity Control DQSXFER DQS Delay Control Bus ...
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... In a typical DDR memory interface design, the phase relationship between the incoming delayed DQS strobe and the internal system clock (during the READ cycle) is unknown. The LatticeXP2 family contains dedicated circuits to transfer data between these domains. To prevent set-up and hold violations, at the domain transfer between DQS (delayed) and the system clock, a clock polarity selector is used ...
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... LVCMOS, SSTL, HSTL, LVDS and LVPECL. sysIO Buffer Banks LatticeXP2 devices have eight sysIO buffer banks for user I/Os arranged two per side. Each bank is capable of sup- porting multiple I/O standards. Each sysIO bank has its own I/O supply voltage (V ...
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... MLVDS, BLVDS, LVPECL, RSDS, differential SSTL and differential HSTL. Tables 2-13 and 2-14 show the I/O stan- dards (together with their supply and reference voltages) supported by LatticeXP2 devices. For further information on utilizing the sysIO buffer to support a variety of standards please see TN1136, LatticeXP2 sysIO Usage Guide. CC supplies ...
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... Differential SSTL25 Class I, II Differential SSTL33 Class I, II Differential HSTL15 Class I Differential HSTL18 Class I, II LVDS, MLVDS, LVPECL, BLVDS, RSDS 1. When not specified, V can be set anywhere in the valid operating range (page 3-1). CCIO LatticeXP2 Family Data Sheet V (Nom.) V REF — — — ...
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... These capabilities make the LatticeXP2 ideal for many multiple power supply and hot-swap applications. IEEE 1149.1-Compliant Boundary Scan Testability All LatticeXP2 devices have boundary scan cells that are accessed through an IEEE 1149.1 compliant Test Access Port (TAP). This allows functional testing of the circuit board, on which the device is mounted, through a serial scan path that can access all critical logic nodes ...
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... Usage Guide. flexiFLASH Device Configuration The LatticeXP2 devices combine Flash and SRAM on a single chip to provide users with flexibility in device pro- gramming and configuration. Figure 2-33 provides an overview of the arrangement of Flash and SRAM configura- tion cells within the device. The remainder of this section provides an overview of these capabilities. See TN1141, LatticeXP2 sysCONFIG Usage Guide, for a more detailed description. Figure 2-33. Overview of Flash and SRAM Confi ...
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... Flash portion of the device. Serial TAG Memory LatticeXP2 devices offer 0.6 to 3.3kbits of Flash memory in the form of Serial TAG memory. The TAG memory is an area of the on-chip Flash that can be used for non-volatile storage including electronic ID codes, version codes, date stamps, asset IDs and calibration settings ...
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... For further information on SED support, please see TN1130, LatticeXP2 Soft Error Detection (SED) Usage Guide. On-Chip Oscillator Every LatticeXP2 device has an internal CMOS oscillator that is used to derive a Master Clock (CCLK) for configu- ration. The oscillator and CCLK run continuously and are available to user logic after configuration is complete. The available CCLK frequencies are listed in Table 2-14 ...
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... Lattice Semiconductor Density Shifting The LatticeXP2 family is designed to ensure that different density devices in the same family and in the same pack- age have the same pinout. Furthermore, the architecture ensures a high success rate when performing design migration from lower density devices to higher density devices. In many cases also possible to shift a lower uti- lization design targeted for a high-density device to a lower density device. However, the exact details of the fi ...
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... Data Retention RETENTION © 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... Specified limits do not apply to the single I/O, PL26B, for the LFXP2-17E-8W 1.0MHz. A Note: Specifications for the LFXP2-17E ‘8W’ are the same as the LFXP2-17E, except as specified above in the Hot Socketing Specifications and DC Electrical Characteristics Tables Condition 0 ≤ V ≤ V (MAX ...
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... Power Supply Current CCJ CCJ 1. For further information on supply current, please see TN1139, Power Estimation and Management for LatticeXP2 Devices. 2. Assumes all outputs are tristated, all inputs are configured as LVCMOS and held at the V 3. Frequency 0MHz. 4. Pattern represents a “blank” configuration data file. ...
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... I VCCJ Power Supply Current CCJ 1. For further information on supply current, please see TN1139, Power Estimation and Management for LatticeXP2 Devices. 2. Assumes all outputs are tristated, all inputs are configured as LVCMOS and held at the V 3. Frequency 0MHz. 4. Does not include additional current from bypass or decoupling capacitor across the supply. ...
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... Power Supply Current CCJ CCJ 1. For further information on supply current, please see TN1139, Power Estimation and Management for LatticeXP2 Devices. 2. Assumes all outputs are tristated, all inputs are configured as LVCMOS and held at the V 3. Frequency 0MHz (excludes dynamic power from FPGA operation). ...
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... CCIO 3-6 DC and Switching Characteristics LatticeXP2 Family Data Sheet V (V) REF Min. Typ. — — — — — — — — — — — — — ...
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... REF - 0.125 V + 0.125 3.6 REF - 0.125 V + 0.125 3.6 REF - 0 0.1 3.6 REF - 0 0.1 3.6 REF - 0 0.1 3.6 REF 3-7 DC and Switching Characteristics LatticeXP2 Family Data Sheet Max. (V) Min. (V) I (mA) OL 20, 16, 0 0.4 CCIO 12 0 0.2 0.1 CCIO 20, 16, 0 0.4 CCIO 12 ...
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... LVDS25E The top and bottom sides of LatticeXP2 devices support LVDS outputs via emulated complementary LVCMOS out- puts in conjunction with a parallel resistor across the driver outputs. The scheme shown in Figure 3-1 is one possi- ble solution for point-to-point signals. ...
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... VCCIO. The default drive current for LVCMOS33D output is 12mA with the option to change the device strength to 4mA, 8mA, 16mA or 20mA. Follow the LVCMOS33 specifications for the DC characteristics of the LVCMOS33D. DC and Switching Characteristics Description Typical 2.50 20 158 140 100 ) 1. 1. 0.35 1 1.25 100.5 6.03 3-9 LatticeXP2 Family Data Sheet Units V Ω Ω Ω Ω Ω mA ...
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... Lattice Semiconductor BLVDS The LatticeXP2 devices support the BLVDS standard. This standard is emulated using complementary LVCMOS outputs in conjunction with a parallel external resistor across the driver outputs. BLVDS is intended for use when multi-drop and bi-directional multi-point differential signaling is required. The scheme shown in Figure 3-2 is one possible solution for bi-directional multi-point differential signals ...
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... Lattice Semiconductor LVPECL The LatticeXP2 devices support the differential LVPECL standard. This standard is emulated using complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The LVPECL input standard is supported by the LVDS differential input buffer. The scheme shown in Figure 3-3 is one possible solution for point- to-point signals ...
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... Lattice Semiconductor RSDS The LatticeXP2 devices support differential RSDS standard. This standard is emulated using complementary LVC- MOS outputs in conjunction with a parallel resistor across the driver outputs. The RSDS input standard is sup- ported by the LVDS differential input buffer. The scheme shown in Figure 3-4 is one possible solution for RSDS standard implementation ...
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... Lattice Semiconductor MLVDS The LatticeXP2 devices support the differential MLVDS standard. This standard is emulated using complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The MLVDS input standard is sup- ported by the LVDS differential input buffer. The scheme shown in Figure 3-5 is one possible solution for MLVDS standard implementation ...
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... DSP Functions 18x18 Multiplier (All Registers) 9x9 Multiplier (All Registers) 36x36 Multiply (All Registers) 18x18 Multiply/Accumulate (Input and Output Registers) 18x18 Multiply-Add/Sub-Sum (All Registers) DC and Switching Characteristics 1 Function Function 3-14 LatticeXP2 Family Data Sheet -7 Timing Units 4.4 ns 5.2 ns 5.6 ns 3 ...
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... Actual delays at nominal temperature and voltage for best case process, can be much better than the values given in the tables. The ispLEVER design tool can provide logic timing numbers at a particular temperature and voltage. DC and Switching Characteristics Function 3-15 LatticeXP2 Family Data Sheet -7 Timing Units 250 MHz 210 ...
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... XP2-17 — XP2-30 — XP2-40 — XP2-5 0.00 XP2-8 0.00 XP2-17 0.00 XP2-30 0.00 XP2-40 0.00 3-16 DC and Switching Characteristics LatticeXP2 Family Data Sheet -6 -5 Max. Min. Max. Min. Max. 3.80 — 4.20 — 3.80 — 4.20 — 3.80 — 4.20 — ...
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... Lattice Semiconductor LatticeXP2 External Switching Characteristics (Continued) Parameter Description Clock to Data Hold - PIO Input t HE Register Clock to Data Setup - PIO Input t SU_DELE Register with Data Input Delay Clock to Data Hold - PIO Input t H_DELE Register with Input Data Delay Clock Frequency of I/O and PFU ...
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... Lattice Semiconductor LatticeXP2 External Switching Characteristics (Continued) Parameter Description Clock to Data Hold - PIO Input t H_DELPLL Register with Input Data Delay 2 3 DDR and DDR2 I/O Pin Parameters Data Valid After DQS t DVADQ (DDR Read) Data Hold After DQS t DVEDQ (DDR Read) ...
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... DC and Switching Characteristics LatticeXP2 Family Data Sheet Min. Max. Min. Max. — 0.238 — 0.260 — 0.399 — 0.494 — 0.769 — 0.818 0.151 — ...
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... DC and Switching Characteristics LatticeXP2 Family Data Sheet 1 (Continued Min. Max. Min. Max. — 0.419 — 0.452 0.035 0.035 0.035 0.035 — 3.142 — ...
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... Max. -0.787 — 4.896 — -1.439 — — 4.513 — 2.153 — 0.569 -0.270 — 0.306 — 3-21 DC and Switching Characteristics LatticeXP2 Family Data Sheet 1 (Continued Min. Max. Min. Max. -0.890 — -0.994 — 5.413 — 5.931 — -1.604 — -1.770 — ...
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... Figure 3-7. Read/Write Mode with Input and Output Registers CLKA CSA WEA ADA t DIA DOA (Regs CO_EBR Invalid Data Mem(n) data from previous read output is only updated during a read cycle 3-22 DC and Switching Characteristics LatticeXP2 Family Data Sheet CO_EBR CO_EBR COO_EBR COO_EBR D1 D0 ...
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... Data from Prev Read DOA or Write Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive edge of the clock. Three consecutive writes ACCESS ACCESS ACCESS D0 D1 3-23 DC and Switching Characteristics LatticeXP2 Family Data Sheet ACCESS ...
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... HSTL18_I HSTL_18 class I 8mA drive HSTL18_II HSTL_18 class II HSTL18D_I Differential HSTL 18 class I 8mA drive HSTL18D_II Differential HSTL 18 class Over Recommended Operating Conditions Description 4 3-24 DC and Switching Characteristics LatticeXP2 Family Data Sheet - -0.26 -0.11 0.04 -0.26 -0.11 0.04 -0.26 -0.11 0.04 -0.26 -0 ...
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... LVCMOS 3.3 12mA drive, slow slew rate LVCMOS33_16mA LVCMOS 3.3 16mA drive, slow slew rate LVCMOS33_20mA LVCMOS 3.3 20mA drive, slow slew rate (Continued) Over Recommended Operating Conditions Description 3-25 DC and Switching Characteristics LatticeXP2 Family Data Sheet - 0.32 0.69 1.06 0.32 0.69 1.06 -0.25 ...
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... All other standards tested according to the appropriate specifications. 4. These timing adders are measured with the recommended resistor values. Timing (Continued) Over Recommended Operating Conditions Description 3-26 DC and Switching Characteristics LatticeXP2 Family Data Sheet - 1.05 1.43 1.81 0.78 1.15 1.52 ...
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... MHz < f < 400 MHz OUT f < 100 MHz OUT N/M = integer At 90 435MHz 10 to 25MHz 90% to 90% 10% to 10% 10% to 90% 3-27 DC and Switching Characteristics LatticeXP2 Family Data Sheet Min. Typ. Max. 10 — 435 10 — 435 0.078 — 217.5 3.3 — ...
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... Lattice Semiconductor LatticeXP2 sysCONFIG Port Timing Specifications Parameter sysCONFIG POR, Initialization and Wake Up t Minimum Vcc to INITN High ICFG t Time from tICFG to valid Master CCLK VMC t PROGRAMN Pin Pulse Rejection PRGMRJ t PROGRAMN Low Time to Start Configuration PRGM t PROGRAMN High to INITN High Delay ...
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... VCC PROGRAMN DONE INITN CSSPIN CCLK SISPI SOSPI Over Recommended Operating Conditions Min. Selected value -30% Selected value +30% 40 Capture CFGx … Opcode 3-29 DC and Switching Characteristics LatticeXP2 Family Data Sheet Max. Units MHz … … 127 128 Address Ignore Valid Bitstream ...
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... Erase Time Flash Density TAG Main Array TAG Main Array TAG Main Array TAG Main Array TAG Main Array 3-30 DC and Switching Characteristics LatticeXP2 Family Data Sheet Typ. Max. — 1.8 2.1 — 1.9 2.3 — 1.7 2.0 — 2.0 2.1 — ...
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... BSCAN test update register, falling edge of clock to valid enable BTUPOEN Timing v. A 0.10 Over Recommended Operating Conditions EBR Density (Bits) Time (Typ.) 166K 221K 276K 387K 885K Over Recommended Operating Conditions Parameter 3-31 DC and Switching Characteristics LatticeXP2 Family Data Sheet Units 1.5 s 1.5 s 1.5 s 2.0 s 3.0 s Min. Max. — ...
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... Figure 3-10. JTAG Port Timing Waveforms TMS TDI t BTCPH TCK TDO Data to be captured from I/O Data to be driven out to I/O DC and Switching Characteristics t t BTS BTH t BTCPL t t BTCO BTCOEN BTCRH t BTCRS Data Captured t t BTUPOEN BUTCO 3-32 LatticeXP2 Family Data Sheet t BTCP t BTCODIS BTUODIS ...
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... Includes Test Fixture and Probe Capacitance ∞ ∞ ∞ 1MΩ ∞ 1MΩ ∞ 100 ∞ 100 3-33 DC and Switching Characteristics LatticeXP2 Family Data Sheet Test Poi nt C Timing Ref. L LVCMOS 3.3 = 1.5V LVCMOS 2 CCIO 0pF LVCMOS 1 CCIO LVCMOS 1 CCIO LVCMOS 1 ...
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... TCK TDI © 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... Chip select in Slave SPI mode. This pin has a weak internal pull-up. Test Output Enable tristates all I/O pins when driven low. This pin has a weak I internal pull-up, but when not used an external pull- mended. 4-2 Pinout Information LatticeXP2 Family Data Sheet Description is recom- CC ...
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... In some packages, all the potential DDR data (DQ) pins may not be available. PIC numbering definitions are provided in the “Signal Names” column of the Signal Descriptions table. LatticeXP2 Family Data Sheet DDR Strobe (DQS) and PIO Within PIC Data (DQ) Pins ...
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... Pinout Information LatticeXP2 Family Data Sheet XP2-17 XP2-30 208 256 484 256 484 672 PQFP ftBGA fpBGA ftBGA fpBGA fpBGA 146 201 358 201 363 472 57 77 135 77 137 180 ...
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... Minimum requirement to implement a fully functional 8-bit wide DDR bus. Available DDR interface consists of at least 12 I/Os (1 DQS + 1 DQSB + 8 DQs + Bank VREF1). Logic Signal Connections Package pinout information can be found under “Data Sheets” on the LatticeXP2 product pages on the Lattice web- site at www.latticesemi.com/products/fpga/xp2 and in the Lattice ispLEVER software. Thermal Management Thermal management is recommended as part of any sound FPGA design methodology. To assess the thermal characteristics of a system, Lattice specifi ...
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... February 2008 Part Number Description LFXP2 – – X XXXXX X XX Device Family XP2 Logic Capacity LUTs LUTs 17 = 17K LUTs 30 = 30K LUTs 40 = 40K LUTs Supply Voltage E = 1.2V Speed 5 = Slowest Fastest Ordering Information The LatticeXP2 devices are marked with a single temperature grade, either Commercial or Industrial, as shown below. © ...
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... Lattice Semiconductor Lead-Free Packaging Part Number Voltage LFXP2-5E-5MN132C 1.2V LFXP2-5E-6MN132C 1.2V LFXP2-5E-7MN132C 1.2V LFXP2-5E-5TN144C 1.2V LFXP2-5E-6TN144C 1.2V LFXP2-5E-7TN144C 1.2V LFXP2-5E-5QN208C 1.2V LFXP2-5E-6QN208C 1.2V LFXP2-5E-7QN208C 1.2V LFXP2-5E-5FTN256C 1.2V LFXP2-5E-6FTN256C 1.2V LFXP2-5E-7FTN256C 1.2V Part Number Voltage LFXP2-8E-5MN132C 1.2V LFXP2-8E-6MN132C 1.2V LFXP2-8E-7MN132C 1.2V LFXP2-8E-5TN144C 1 ...
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... Initial production devices. Refer to the Hot Socketing Specifications Table and DC Electrical Characteristics Table in this data sheet for I/O leakage current specifications. Part Number Voltage LFXP2-30E-5FTN256C 1.2V LFXP2-30E-6FTN256C 1.2V LFXP2-30E-7FTN256C 1.2V LFXP2-30E-5FN484C 1.2V LFXP2-30E-6FN484C 1.2V LFXP2-30E-7FN484C 1.2V LFXP2-30E-5FN672C 1.2V LFXP2-30E-6FN672C 1.2V LFXP2-30E-7FN672C 1.2V Part Number Voltage LFXP2-40E-5FN484C 1 ...
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... LFXP2-8E-5QN208I 1.2V LFXP2-8E-6QN208I 1.2V LFXP2-8E-5FTN256I 1.2V LFXP2-8E-6FTN256I 1.2V Part Number Voltage 1 LFXP2-17E-5QN208I8W 1.2V 1 LFXP2-17E-6QN208I8W 1.2V 1 LFXP2-17E-5FTN256I8W 1.2V 1 LFXP2-17E-6FTN256I8W 1.2V 1 LFXP2-17E-5FN484I8W 1.2V 1 LFXP2-17E-6FN484I8W 1.2V LFXP2-17E-5QN208I 1.2V LFXP2-17E-6QN208I 1.2V LFXP2-17E-5FTN256I 1.2V LFXP2-17E-6FTN256I 1.2V LFXP2-17E-5FN484I 1.2V LFXP2-17E-6FN484I 1.2V 1. Initial production devices. Refer to the Hot Socketing Specifications Table and DC Electrical Characteristics Table in this data sheet for I/O leakage current specifi ...
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... Lattice Semiconductor Part Number Voltage LFXP2-30E-5FTN256I 1.2V LFXP2-30E-6FTN256I 1.2V LFXP2-30E-5FN484I 1.2V LFXP2-30E-6FN484I 1.2V LFXP2-30E-5FN672I 1.2V LFXP2-30E-6FN672I 1.2V Part Number Voltage LFXP2-40E-5FN484I 1.2V LFXP2-40E-6FN484I 1.2V LFXP2-40E-5FN672I 1.2V LFXP2-40E-6FN672I 1.2V LatticeXP2 Family Data Sheet Grade Package Pins -5 Lead-Free ftBGA 256 -6 Lead-Free ftBGA 256 ...
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... LFXP2-8E-6FT256C LFXP2-8E-7FT256C Part Number 1 LFXP2-17E-5FT256C8W 1 LFXP2-17E-6FT256C8W 1 LFXP2-17E-7FT256C8W 1 LFXP2-17E-5F484C8W 1 LFXP2-17E-6F484C8W 1 LFXP2-17E-7F484C8W LFXP2-17E-5FT256C LFXP2-17E-6FT256C LFXP2-17E-7FT256C LFXP2-17E-5F484C LFXP2-17E-6F484C LFXP2-17E-7F484C 1. Initial production devices. Refer to the Hot Socketing Specifications Table and DC Electrical Characteristics Table in this data sheet for I/O leakage current specifications. Commercial Voltage ...
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... Lattice Semiconductor Part Number LFXP2-30E-5FT256C LFXP2-30E-6FT256C LFXP2-30E-7FT256C LFXP2-30E-5F484C LFXP2-30E-6F484C LFXP2-30E-7F484C LFXP2-30E-5F672C LFXP2-30E-6F672C LFXP2-30E-7F672C Part Number LFXP2-40E-5F484C LFXP2-40E-6F484C LFXP2-40E-7F484C LFXP2-40E-5F672C LFXP2-40E-6F672C LFXP2-40E-7F672C Part Number LFXP2-5E-5M132I LFXP2-5E-6M132I LFXP2-5E-6FT256I Part Number LFXP2-8E-5M132I LFXP2-8E-6M132I LFXP2-5E-5FT256I LFXP2-8E-5FT256I LFXP2-8E-6FT256I Voltage Grade Package 1.2V -5 ftBGA 1.2V -6 ftBGA 1.2V -7 ftBGA 1 ...
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... LFXP2-17E-5F484I LFXP2-17E-6F484I 1. Initial production devices. Refer to the Hot Socketing Specifications Table and DC Electrical Characteristics Table in this data sheet for I/O leakage current specifications. Part Number LFXP2-30E-5FT256I LFXP2-30E-6FT256I LFXP2-30E-5F484I LFXP2-30E-6F484I LFXP2-30E-5F672I LFXP2-30E-6F672I Part Number LFXP2-40E-5F484I LFXP2-40E-6F484I LFXP2-40E-5F672I LFXP2-40E-6F672I Voltage Grade Package 1 ...
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... PCI: www.pcisig.com © 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... DC and Switching Characteristics © 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... Removed Read-Before-Write sysMEM EBR mode. Clarification of the operation of the secondary clock regions. Removed Read-Before-Write sysMEM EBR mode. Updated DDR Banks Bonding Out per I/O Bank section of Pin Informa- tion Summary Table. 7-2 Revision History LatticeXP2 Family Data Sheet Change Summary ...